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when E i 1 À E i 2 is either slightly positive or negative, the actual value set by the threshold voltage E T .
The saturation output value E sat is nearly the supply voltage E s . For example, a 741 op-amp driven at
Æ15 V might saturate at Æ13.5 V. The value for E T can be adjusted by the amplifier bias (offset null)
voltage E bias . The comparator output is given by
E o ¼ A o E i 1 À E i 2
ð
Þ
¼ þE sat
¼ ÀE sat
for
for
for
E i 1 À E i 2
E T
E i 1 À E i 2 > E T
E i 1 À E i 2 < ÀE T
ð6:54Þ
This input–output relation is shown in Figure 6.21b. For a Æ15 V supply and a gain of about
200,000, the comparator might saturate with a voltage difference of only $68 mV.
Often E i 2 is a known reference voltage. This allows the comparator output to be used for control
circuits to decide if E i 1 is less than or greater than E i 2 ; a positive difference gives a positive output.
One frequent use of the comparator is in an analog-to-digital converter (see Chapter 7). A zenerdiode connected between the þ input and the output provides a TTL(transistor-transistor logic)
compatible output signal for digital system use.
Sample-and-Hold Circuit
The sample-and-hold circuit (SHC) is used to take a narrow-band measurement of a time-changing
signal and to hold that measured value until reset. It is widely used in data acquisition systems using
analog-to-digital converters. The circuit tracks the signal until it is triggered to hold it at a fixed value
while measuring it. This is illustrated in Figure 6.22a, in which the track-and-hold logic provides
the appropriate trigger.
The basic circuit for sample and hold is shown in Figure 6.22b. The switch S 1 is a fast analog
device. When the switch is closed, the ‘‘hold’’ capacitor C is charged through the source resistor R s .
When the capacitor is charged, the switch is opened. The amplifier presents a very high input
impedance and very low current, which, together with a very low leakage capacitor, allows for a
sufficiently long hold time. The typical SHC is noninverting with a unit gain (G ¼ 1).
+E bias –E bias
E i 1
E i 2
E o
(a) Differential amplifier
E o
output
E sat
–E sat
–E T
E T
E i 1
– E i 2
(b) Input–output scheme
G(E i 1
– E i 2
)
Input
+
–
Figure 6.21 Analog voltage comparator.
6.7 Analog Signal Conditioning: Special-Purpose Circuits 235
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