3.2 Digital Implementation
45
Heartbeat
packet generator
Link sync
packet generator
Serializer x11
Data
ready
Read
enable Data
Channel
ring buffer
Pre-trigger buffer
Baseline
Correction 1
Tail
cancellation
Baseline
Correction 2
Baseline
Correction 3
Zero
suppression
Data formatting
Huffman
ADC input
Channel registers
x32
Global registers
I
2
C slow control
Event manager
I
2
C signals
Chip address
Reset manager
Trigger distributor
Clock manager
Clocks
Clock config.
Hard reset
Power-on reset
HB trigger
BX sync trigger
Event trigger
Bunch crossing
counter
Serial
out
HB trigger
BX sync
trigger
Event
trigger
Daisy chain
delay compensation
Buffer full
Serial input
Registers
Channel register control
Various global settings
Event control and trigger count
BX control and BX count
BX count
Event control
Soft reset
Daisy chain
control
Resets
Link sync
reg
Registers
2
10
10
13
13
13
Filters
13
Ctrl
Ctrl
13
Ctrl
JTAG
BX count
Daisy chain
ring buffer
Channel
ordering
Neighbour buffer full
Direct ADC serializer
Digital clocks
ADC
clocks
20
Ctrl
Wishbone
bus
11
Fig. 3.4
Simplified block diagram of the digital design. Some independently operating test features are not shown for clarity