2.4 Digital Specification
29
When using an externally provided trigger signal, it is often beneficial to be able
to compensate for the delay between the trigger generator and the reception of the
trigger signal on the device. This compensation is done by delaying the incoming
data by the same amount as the trigger signal is delayed. This can also be used for
looking at data prior to the triggering event by adding more delay. Implementing
a programmable length delay chain of 192 samples satisfies the requirement of the
TPC. The maximum delay configuration corresponds to a compensation of 19.2 µs
at a sampling frequency of 10 MHz.
The particles travelling around the acceleration ring of the LHC are grouped in
bunches and spaced apart by about 25 ns providing the 40 MHz that is distributed and
used as the base frequency in many of the devices operating in the LHC, among other
the GBTx. The SAMPA device has an internal 20-bit counter that runs at 40 MHz
independently of the configured ADC sampling frequency. At the start of each new
event, the value of this counter is captured and it is added to the header of that event
as the event’s bunch crossing id. If the ADC sampling clock is derived from the same
source clock as the 40 MHz clock it is possible to use this value as an event number
id by calculating :
event num =
B X I D
event length ·
40 M H z
F s
(2.1)
Where B X I D is the bunch-crossing id from the header, event length is the preprogrammed length of the event and F s is the ADC sampling frequency.
On reception of an external bunch-crossing sync-trigger, the counter will be reset.
This makes it possible to align the bunch-crossing id across different SAMPA chips.
For off-site synchronization, grouping of events, and to verify that a device is
alive, a specially crafted heartbeat packet will be generated once a heartbeat trigger
signal is received. The packet contains among other things the bunch-crossing id
when the trigger arrived and the chip address.
2.4.2 Interfacing
The clock for the device is provided from the GBTx, which can provide clock frequencies relative to the link speed that is configured for a link, e.g. it will provide
80 MHz, 160 MHz and 320 MHz for 80 Mbps, 160 Mbps and 320 Mbps links. The
operational clocks need to be derived inside the device. Since the clocks provided
from the GBTx are synchronous to the LHC clock, the sampling clock of the ADC
will then also be synchronous to this clock. For use with other detectors, an option
for externally provided clocks is necessary.
The reset and trigger signal are connected to the GBTx and can be supplied to
multiple devices in a multi-drop fashion. As the signals are pulse based, they can
be transmitted at a lower data rate through the GBTx if needed. Higher speeds are
29
When using an externally provided trigger signal, it is often beneficial to be able
to compensate for the delay between the trigger generator and the reception of the
trigger signal on the device. This compensation is done by delaying the incoming
data by the same amount as the trigger signal is delayed. This can also be used for
looking at data prior to the triggering event by adding more delay. Implementing
a programmable length delay chain of 192 samples satisfies the requirement of the
TPC. The maximum delay configuration corresponds to a compensation of 19.2 µs
at a sampling frequency of 10 MHz.
The particles travelling around the acceleration ring of the LHC are grouped in
bunches and spaced apart by about 25 ns providing the 40 MHz that is distributed and
used as the base frequency in many of the devices operating in the LHC, among other
the GBTx. The SAMPA device has an internal 20-bit counter that runs at 40 MHz
independently of the configured ADC sampling frequency. At the start of each new
event, the value of this counter is captured and it is added to the header of that event
as the event’s bunch crossing id. If the ADC sampling clock is derived from the same
source clock as the 40 MHz clock it is possible to use this value as an event number
id by calculating :
event num =
B X I D
event length ·
40 M H z
F s
(2.1)
Where B X I D is the bunch-crossing id from the header, event length is the preprogrammed length of the event and F s is the ADC sampling frequency.
On reception of an external bunch-crossing sync-trigger, the counter will be reset.
This makes it possible to align the bunch-crossing id across different SAMPA chips.
For off-site synchronization, grouping of events, and to verify that a device is
alive, a specially crafted heartbeat packet will be generated once a heartbeat trigger
signal is received. The packet contains among other things the bunch-crossing id
when the trigger arrived and the chip address.
2.4.2 Interfacing
The clock for the device is provided from the GBTx, which can provide clock frequencies relative to the link speed that is configured for a link, e.g. it will provide
80 MHz, 160 MHz and 320 MHz for 80 Mbps, 160 Mbps and 320 Mbps links. The
operational clocks need to be derived inside the device. Since the clocks provided
from the GBTx are synchronous to the LHC clock, the sampling clock of the ADC
will then also be synchronous to this clock. For use with other detectors, an option
for externally provided clocks is necessary.
The reset and trigger signal are connected to the GBTx and can be supplied to
multiple devices in a multi-drop fashion. As the signals are pulse based, they can
be transmitted at a lower data rate through the GBTx if needed. Higher speeds are