142
Appendix B: Registers
B.1.4 Channel Ordering
The channel ordering is kept as an ordered list of channels. The order of the channels
in the list defines the order that the channels will be read out in. Subsequently, it
also defines the serial link that a channel will be read out on, see Table B.4. Note
that reading and writing to CHORDAT does not necessarily talk to the same register.
When you read from CHORDAT, you read directly from the register that CHORDCTL[4:0] is pointing to. Writing to CHORDAT writes to a temporary register and the
data in this register is only moved to the address that CHORDCTL[4:0] is pointing
to when the write command CHORDCTL[5] is set high.
Write
1. Set the channel number that you want to place in the list at CHORDAT (Channel
ordering data).
2. Set CHORDCTL[5] (Channel ordering control) high for write and set CHORDCTL[4:0] to the position in the list that you want to place the channel in.
Read
1. Set CHORDCTL[4:0] to the position in the list that you want to read from.
2. The data will appear at CHORDAT.
B.1.5 ADC Configuration
These registers enable configuration of some aspects of the ADC operation.
ADCDEL (ADC delay) As shown in Fig. 3.5 there is available a possibility to
delay the clock supplied to the ADCs (ckoutADCanalog) in relation to the clock
for the digital part (ckoutADC). This feature could be used to reduce the influence
of the digital part switching noise on the ADC sampling. The phase can be changed
by with a selection of ca. 1.5 ns up to ca. 94.5 ns depending on process variations,
which amounts to almost a full cycle at the minimum designed for ADC clock
speed of 10 MHz. If bit [6] is enabled the clock is also inverted, which gives a
less process dependent phase shift.
ADCTRIM (ADC trimming) Sets the configuration for the Configurable Reference Voltage Source for the analogue front-end which adjusts the v450, v600 and
v750.
B.1.6 Serial link configuration
These registers enable configuration of the serial link driver and receivers.
Appendix B: Registers
B.1.4 Channel Ordering
The channel ordering is kept as an ordered list of channels. The order of the channels
in the list defines the order that the channels will be read out in. Subsequently, it
also defines the serial link that a channel will be read out on, see Table B.4. Note
that reading and writing to CHORDAT does not necessarily talk to the same register.
When you read from CHORDAT, you read directly from the register that CHORDCTL[4:0] is pointing to. Writing to CHORDAT writes to a temporary register and the
data in this register is only moved to the address that CHORDCTL[4:0] is pointing
to when the write command CHORDCTL[5] is set high.
Write
1. Set the channel number that you want to place in the list at CHORDAT (Channel
ordering data).
2. Set CHORDCTL[5] (Channel ordering control) high for write and set CHORDCTL[4:0] to the position in the list that you want to place the channel in.
Read
1. Set CHORDCTL[4:0] to the position in the list that you want to read from.
2. The data will appear at CHORDAT.
B.1.5 ADC Configuration
These registers enable configuration of some aspects of the ADC operation.
ADCDEL (ADC delay) As shown in Fig. 3.5 there is available a possibility to
delay the clock supplied to the ADCs (ckoutADCanalog) in relation to the clock
for the digital part (ckoutADC). This feature could be used to reduce the influence
of the digital part switching noise on the ADC sampling. The phase can be changed
by with a selection of ca. 1.5 ns up to ca. 94.5 ns depending on process variations,
which amounts to almost a full cycle at the minimum designed for ADC clock
speed of 10 MHz. If bit [6] is enabled the clock is also inverted, which gives a
less process dependent phase shift.
ADCTRIM (ADC trimming) Sets the configuration for the Configurable Reference Voltage Source for the analogue front-end which adjusts the v450, v600 and
v750.
B.1.6 Serial link configuration
These registers enable configuration of the serial link driver and receivers.