Appendix A
Schematic Legends
Some simplifications have been done in the schematic drawings to avoid redundancy
and make them easier to read. The custom/uncommon symbols are shown in Fig.
A.1.
1
8
OR-reduce A = |B
<>1
9
8
Extend 1 bit A = {1'b0,B}
><1
7
8
Reduce 1 bit A = B[7:0]
<>1s
9
8
Sign extend 1 bit A = {B[7],B}
[7:6]
2
8
Extract range A = B[7:6]
<<2
8
8
Logical shift left A = B<<2
>>2
8
8
Logical shift right A = B>>2
Arithmetic shift right A = B>>>C
>>s
8
8
2
AND-reduce A = &B
8
1
XOR-reduce A = ^B
1
8
Fig. A.1 Schematic legend
© The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer
Nature Switzerland AG 2021
A. Velure, A Digital Signal Processor for Particle Detectors, Springer Theses,
https://doi.org/10.1007/978-3-030-71559-5
133