128
5 Conclusion and Outlook
Going with a simplified front-end design would not likely have saved more than
a few months in the SAMPA design process, as the digital design was not one of
the bottlenecks. However, it would have reduced the time needed to test each device
by several minutes in the final production test, which saves some additional months
since there is a need to test 80 000 devices. A smaller device also provides better
yield, possibly lowering the number of wafers, and so lowering costs.
The DSP part benefits from processing many channels as resources can be shared
and so the size of the design can be reduced. With a simplified front-end device, this
benefit is less pronounced, which presents the option of going back to a design with
only 16 channels. This simplifies the analogue layout work and reduces channel-tochannel variations. This could also have significantly reduced the analogue design
time and provided a device at an earlier date, as well as giving even better yields at the
cost of occupying more board area. However, a 16-channel device is a disadvantage
for the MCH as their board area is sparse.
In the case of the MCH, where the area occupied by the devices and its power
consumption is a counter argument to using FPGAs, it would have been possible to
design a separate custom dedicated ASIC only for the digital processing functionality.
As the MCH currently only uses a small part of the functionality of the SAMPA, the
size of the simplified front-end device combined with a new device that replicates
the needed MCH functionality would still likely be smaller and consume less power
than the current device. The primary area and power consumption of the current
device origins from the large buffer memories originally required by the TPC. Since
the MCH only needs 64 channels per board, the device could have been built to
accept data from two 32-channel devices or four 16-channel devices. This would
have saved the effort of developing and testing the daisy chaining implementation
as well. In total, the development time could likely have been reduced to two years
for this device. But, considering that two different devices need to be manufactured,
this solution might not be a cheaper option than the SAMPA.
The other detectors, apart from the TPC and MCH, that are interested in the device
and require more compression or filtering capabilities could utilize an FPGA, which
provides more flexibility to adapt the design to their present needs and gives them an
option of doing upgrades of the firmware code in the future. Additionally, it opens
the possibility to offload the data through the use of high speeds transceivers that
can reach data rates that are higher then what is available with the GBTx. This has
an additional advantage of lowering the needed number of optical fibres, as well as
the cost. However, the use of commercial devices in an irradiated area will always
have the disadvantage that the devices need to be qualified for operation and that the
firmware code for the FPGA needs to be designed with SEE effects in mind.
It was decided not to use Huffman compression with differential encoding for the
TPC readout, as the compression factor was believed to be too much dependent on
detector properties such as noise, baseline instabilities and gain variations compared
to conventional zero suppression [8]. This is in essence true, in the general sense [9],
but it strongly depends on the signal properties of the detector, which were not
known at the time of analysis. The strength of the zero suppression is based on a
stable baseline, which requires the baseline correction functionality to be enabled.
5 Conclusion and Outlook
Going with a simplified front-end design would not likely have saved more than
a few months in the SAMPA design process, as the digital design was not one of
the bottlenecks. However, it would have reduced the time needed to test each device
by several minutes in the final production test, which saves some additional months
since there is a need to test 80 000 devices. A smaller device also provides better
yield, possibly lowering the number of wafers, and so lowering costs.
The DSP part benefits from processing many channels as resources can be shared
and so the size of the design can be reduced. With a simplified front-end device, this
benefit is less pronounced, which presents the option of going back to a design with
only 16 channels. This simplifies the analogue layout work and reduces channel-tochannel variations. This could also have significantly reduced the analogue design
time and provided a device at an earlier date, as well as giving even better yields at the
cost of occupying more board area. However, a 16-channel device is a disadvantage
for the MCH as their board area is sparse.
In the case of the MCH, where the area occupied by the devices and its power
consumption is a counter argument to using FPGAs, it would have been possible to
design a separate custom dedicated ASIC only for the digital processing functionality.
As the MCH currently only uses a small part of the functionality of the SAMPA, the
size of the simplified front-end device combined with a new device that replicates
the needed MCH functionality would still likely be smaller and consume less power
than the current device. The primary area and power consumption of the current
device origins from the large buffer memories originally required by the TPC. Since
the MCH only needs 64 channels per board, the device could have been built to
accept data from two 32-channel devices or four 16-channel devices. This would
have saved the effort of developing and testing the daisy chaining implementation
as well. In total, the development time could likely have been reduced to two years
for this device. But, considering that two different devices need to be manufactured,
this solution might not be a cheaper option than the SAMPA.
The other detectors, apart from the TPC and MCH, that are interested in the device
and require more compression or filtering capabilities could utilize an FPGA, which
provides more flexibility to adapt the design to their present needs and gives them an
option of doing upgrades of the firmware code in the future. Additionally, it opens
the possibility to offload the data through the use of high speeds transceivers that
can reach data rates that are higher then what is available with the GBTx. This has
an additional advantage of lowering the needed number of optical fibres, as well as
the cost. However, the use of commercial devices in an irradiated area will always
have the disadvantage that the devices need to be qualified for operation and that the
firmware code for the FPGA needs to be designed with SEE effects in mind.
It was decided not to use Huffman compression with differential encoding for the
TPC readout, as the compression factor was believed to be too much dependent on
detector properties such as noise, baseline instabilities and gain variations compared
to conventional zero suppression [8]. This is in essence true, in the general sense [9],
but it strongly depends on the signal properties of the detector, which were not
known at the time of analysis. The strength of the zero suppression is based on a
stable baseline, which requires the baseline correction functionality to be enabled.