108
4 Verification and Testing
common Avalon bus [24] along with the microprocessor. The bus can be accessed
directly by the control program on the computer through a custom UART to Avalon
bus bridge. A switch controlled multiplexer facilitates switching between having a
serial connection (UART) to the bus system or to one of the Linux serial terminals,
so the computer can access the Linux system for debugging purposes.
4.2.1.1 Command and Control
The Command and Control unit acts as the bridge between the computer and the
SAMPA for slow control handling and pin control. It also operates as the main control
unit for the surrounding sub-modules. This includes a master I
2 C unit for the slow
control communication, a module for reset generation and event trigger handling,
and other modules for control and running of specialized tests on the SAMPA, such
as a tester for the memory Built-In Self-Test and triangle/saw/sine wave generators
for data path testing on the v1 SAMPA.
4.2.1.2 Data Manager
The data readout from the SAMPA requires a high bandwidth readout system. The
first version of the SAMPA chip can operate three serial links running at only
160 Mbps, but the final version can operate with 11 serial data links running at
320 Mbps each, adding up to 3.52 Gbps total.
The first task of the Data Manager is to synchronize and de-serialize the data
from each link into their native 10-bit word segmentation, verify the parity of the
header, determine the length of the payload that follows and filter out any sync/filler
packages so that they are not sent on. The valid de-serialized packets are further
packed into 64-bit words to make processing on a 32/64 bit system more efficient.
The packets are then further aggregated from the 11 de-serializers into four memorywriter modules via individual buffers. Each memory-writer module is connected to a
separate high-speed 64-bit 100 MHz bus that interfaces to a 400 MHz DDR memory
shared with the microprocessor. The FPGA fabric can thus support writing of the
full 3.52 Gbps to memory. The complete system readout speed is primarily limited
by the throughput of the microprocessor system.
For the second prototype of the SAMPA, the mezzanine cards have been fitted with
two SFP connectors that are connected to high-speed transceivers on the FPGA. By
utilizing two DAQ setups, it would be possible to offload half of the received data to
another DAQ system to increase the collective bandwidth, or they could be interfaced
directly to the CRU once it is available. This option was eventually not utilized, as
reading out large amounts of raw data over a long period of time was not needed.
The system can be set up to acquire data continuously or to acquire a configurable
number of consecutive packets per serial data link. In case an overflow in the buffers
or the memory is detected, the system will drop the payload of the packet and set an
overflow bit in the header, indicating to the data analysis program that the amount of
4 Verification and Testing
common Avalon bus [24] along with the microprocessor. The bus can be accessed
directly by the control program on the computer through a custom UART to Avalon
bus bridge. A switch controlled multiplexer facilitates switching between having a
serial connection (UART) to the bus system or to one of the Linux serial terminals,
so the computer can access the Linux system for debugging purposes.
4.2.1.1 Command and Control
The Command and Control unit acts as the bridge between the computer and the
SAMPA for slow control handling and pin control. It also operates as the main control
unit for the surrounding sub-modules. This includes a master I
2 C unit for the slow
control communication, a module for reset generation and event trigger handling,
and other modules for control and running of specialized tests on the SAMPA, such
as a tester for the memory Built-In Self-Test and triangle/saw/sine wave generators
for data path testing on the v1 SAMPA.
4.2.1.2 Data Manager
The data readout from the SAMPA requires a high bandwidth readout system. The
first version of the SAMPA chip can operate three serial links running at only
160 Mbps, but the final version can operate with 11 serial data links running at
320 Mbps each, adding up to 3.52 Gbps total.
The first task of the Data Manager is to synchronize and de-serialize the data
from each link into their native 10-bit word segmentation, verify the parity of the
header, determine the length of the payload that follows and filter out any sync/filler
packages so that they are not sent on. The valid de-serialized packets are further
packed into 64-bit words to make processing on a 32/64 bit system more efficient.
The packets are then further aggregated from the 11 de-serializers into four memorywriter modules via individual buffers. Each memory-writer module is connected to a
separate high-speed 64-bit 100 MHz bus that interfaces to a 400 MHz DDR memory
shared with the microprocessor. The FPGA fabric can thus support writing of the
full 3.52 Gbps to memory. The complete system readout speed is primarily limited
by the throughput of the microprocessor system.
For the second prototype of the SAMPA, the mezzanine cards have been fitted with
two SFP connectors that are connected to high-speed transceivers on the FPGA. By
utilizing two DAQ setups, it would be possible to offload half of the received data to
another DAQ system to increase the collective bandwidth, or they could be interfaced
directly to the CRU once it is available. This option was eventually not utilized, as
reading out large amounts of raw data over a long period of time was not needed.
The system can be set up to acquire data continuously or to acquire a configurable
number of consecutive packets per serial data link. In case an overflow in the buffers
or the memory is detected, the system will drop the payload of the packet and set an
overflow bit in the header, indicating to the data analysis program that the amount of