4.1 Functional Verification of the Digital Design
105
while running the normal verification testbench. Due to time constraints and lack of
automatic tools to do the verification, this was not completed, though the irradiation
test did not directly uncover any issues that could have been solved by fault injection.
In addition to being able to predict the failure rate of the design, fault injection
can also be utilized for improving mitigation strategies by highlighting areas of the
design that are more sensitive to failures than others. As the TMR technique that
has been employed for SEU protection requires significant area, the test could have
also helped determine areas that could run without TMR or that could employ other
methods of protection, reducing the needed chip area of the digital part.
The testing of the top-level digital design was, due to time constraints, primarily done by directed functional testing of the functionality that the TPC and MCH
required and so certain aspects of the design that are outside the scope of their
requirements will not have been covered. The remaining effort lies in implementing
models of the yet to be tested circuitry so that more of the design can be tested with
randomized testing.
4.2 Hardware Verification of the Digital Design
To verify the various performance specification of the SAMPA, a continuous Data
Acquisition (DAQ) system has been developed. The FPGA-based DAQ system is
specially designed for the qualification of the SAMPA and is designed around an
Altera SocKit [16] evaluation board containing an Altera Cyclone V System-on-Chip
FPGA [17], which has a built-in dual-core ARM
4 Cortex-A9 microprocessor unit.
The SAMPA is mounted on a separate mezzanine board connected to the development
board through a high-speed connector. Control of the SAMPA and the FPGA board
is handled through a Universal Asynchronous Receiver/Transmitter (UART) connection from the controlling computer. Data packets from the SAMPA are acquired
by the FPGA and transmitted verbatim to the readout computer via Gigabit Ethernet.
A block diagram of the system design is shown in Fig. 4.4.
The intention of the DAQ system is to provide an easily customizable, stand-alone
platform that is both compact and easily deployable to multiple testing groups for
analogue behaviour qualification, digital verification, testing of the radiation tolerance and mass production testing. For the radiation tolerance testing, the intention is
to verify the device performance in regards to SEUs, SELs, and functional interrupts.
For the mass production, the goal is to filter out bad devices before mounting them
on front-end cards. DAQ systems and testbenches for the intention of qualifying
of ASICs are commonly designed for a single or a limited set of tests. The system
presented here is on the other hand designed as a common versatile platform and
framework to interface with the SAMPA ASIC for a multitude of tests.
A custom DAQ solution was chosen due to a number of reasons. The SAMPA uses
SLVS differential links [18] for its high-speed serial communication links, since this
4 Advanced RISC Machine.
105
while running the normal verification testbench. Due to time constraints and lack of
automatic tools to do the verification, this was not completed, though the irradiation
test did not directly uncover any issues that could have been solved by fault injection.
In addition to being able to predict the failure rate of the design, fault injection
can also be utilized for improving mitigation strategies by highlighting areas of the
design that are more sensitive to failures than others. As the TMR technique that
has been employed for SEU protection requires significant area, the test could have
also helped determine areas that could run without TMR or that could employ other
methods of protection, reducing the needed chip area of the digital part.
The testing of the top-level digital design was, due to time constraints, primarily done by directed functional testing of the functionality that the TPC and MCH
required and so certain aspects of the design that are outside the scope of their
requirements will not have been covered. The remaining effort lies in implementing
models of the yet to be tested circuitry so that more of the design can be tested with
randomized testing.
4.2 Hardware Verification of the Digital Design
To verify the various performance specification of the SAMPA, a continuous Data
Acquisition (DAQ) system has been developed. The FPGA-based DAQ system is
specially designed for the qualification of the SAMPA and is designed around an
Altera SocKit [16] evaluation board containing an Altera Cyclone V System-on-Chip
FPGA [17], which has a built-in dual-core ARM
4 Cortex-A9 microprocessor unit.
The SAMPA is mounted on a separate mezzanine board connected to the development
board through a high-speed connector. Control of the SAMPA and the FPGA board
is handled through a Universal Asynchronous Receiver/Transmitter (UART) connection from the controlling computer. Data packets from the SAMPA are acquired
by the FPGA and transmitted verbatim to the readout computer via Gigabit Ethernet.
A block diagram of the system design is shown in Fig. 4.4.
The intention of the DAQ system is to provide an easily customizable, stand-alone
platform that is both compact and easily deployable to multiple testing groups for
analogue behaviour qualification, digital verification, testing of the radiation tolerance and mass production testing. For the radiation tolerance testing, the intention is
to verify the device performance in regards to SEUs, SELs, and functional interrupts.
For the mass production, the goal is to filter out bad devices before mounting them
on front-end cards. DAQ systems and testbenches for the intention of qualifying
of ASICs are commonly designed for a single or a limited set of tests. The system
presented here is on the other hand designed as a common versatile platform and
framework to interface with the SAMPA ASIC for a multitude of tests.
A custom DAQ solution was chosen due to a number of reasons. The SAMPA uses
SLVS differential links [18] for its high-speed serial communication links, since this
4 Advanced RISC Machine.