104
4 Verification and Testing
Since the ADC requires clocks with a low amount of jitter, the clock generator
was simulated on the layout level in circuit simulation and was found to have less
than 50 ps of added jitter on the ADC sampling clock.
4.1.3.3 Mixed-Signal Verification
Mixed-signal verification
3 involves connecting the analogue circuitry together with
the digital to verify that communication between the analogue and digital works as
expected. Since the chip has been created with an analogue-on-top flow, i.e. the fully
placed-and-routed digital design is instantiated as a block on the top-level analogue
layout, there is a need to verify that the correct signals have been connected to the
correct ports on the digital design.
To speed up the debugging, the Analogue Mixed-Signal (AMS) verification is
usually done in three stages. Firstly, a behavioural model of the analogue components
is created in either Verilog-AMS or VHDL-AMS, which can then be simulated
together with the digital code at higher simulation speeds. This verifies primarily the
interaction between the various parts.
Since the analogue behavioural model is only a simplification, there is also a
need to do verification with the schematic netlist of the analogue to check that their
behaviour is the same. These tests need to be kept short due to the increased time
needed to run the analogue netlist simulations. Here a few samples have been tested
through the direct serialization mode, through the normal packet based mode and the
daisy-chained mode.
The tests also need to be run with the digital gate level code with back annotated
timing, together with the layout version of the analogue, to verify that the timing
between the ADC and the digital is in order and that the power-up sequencing is
working as it should.
The mixed signal verification helped to uncover issues with signals between the
ADC and digital having inverse direction, start-up issues related to the clock gating
employed in the direct serialization mode and timing issues between the ADC and
digital inputs.
4.1.4 Test Coverage Improvements
As explained in Sect. 4.3.4, an irradiation test was performed on the design to verify
its tolerance to SEUs, but since it is difficult to do an exhaustive test of the failure rate
of the design in all possible configurations during a beam test, a simulation-based
effort to evaluate the effectiveness of the SEU protection could have been of benefit.
This is commonly done by modifying the test environment to support fault injection
3 AMS simulations conducted by Tiago Weber for v2 and Heiner Alarcon for v3, University of São
Paulo, Brazil.
4 Verification and Testing
Since the ADC requires clocks with a low amount of jitter, the clock generator
was simulated on the layout level in circuit simulation and was found to have less
than 50 ps of added jitter on the ADC sampling clock.
4.1.3.3 Mixed-Signal Verification
Mixed-signal verification
3 involves connecting the analogue circuitry together with
the digital to verify that communication between the analogue and digital works as
expected. Since the chip has been created with an analogue-on-top flow, i.e. the fully
placed-and-routed digital design is instantiated as a block on the top-level analogue
layout, there is a need to verify that the correct signals have been connected to the
correct ports on the digital design.
To speed up the debugging, the Analogue Mixed-Signal (AMS) verification is
usually done in three stages. Firstly, a behavioural model of the analogue components
is created in either Verilog-AMS or VHDL-AMS, which can then be simulated
together with the digital code at higher simulation speeds. This verifies primarily the
interaction between the various parts.
Since the analogue behavioural model is only a simplification, there is also a
need to do verification with the schematic netlist of the analogue to check that their
behaviour is the same. These tests need to be kept short due to the increased time
needed to run the analogue netlist simulations. Here a few samples have been tested
through the direct serialization mode, through the normal packet based mode and the
daisy-chained mode.
The tests also need to be run with the digital gate level code with back annotated
timing, together with the layout version of the analogue, to verify that the timing
between the ADC and the digital is in order and that the power-up sequencing is
working as it should.
The mixed signal verification helped to uncover issues with signals between the
ADC and digital having inverse direction, start-up issues related to the clock gating
employed in the direct serialization mode and timing issues between the ADC and
digital inputs.
4.1.4 Test Coverage Improvements
As explained in Sect. 4.3.4, an irradiation test was performed on the design to verify
its tolerance to SEUs, but since it is difficult to do an exhaustive test of the failure rate
of the design in all possible configurations during a beam test, a simulation-based
effort to evaluate the effectiveness of the SEU protection could have been of benefit.
This is commonly done by modifying the test environment to support fault injection
3 AMS simulations conducted by Tiago Weber for v2 and Heiner Alarcon for v3, University of São
Paulo, Brazil.