4.1 Functional Verification of the Digital Design
101
Test
sequencer
SAMPA 1
SAMPA 2
11x Checker
Checker
32x Data
generators
32x Data
generators
Behavioural
model
Behavioural
model
Daisy chain
link
11x serial links
Slow control
Clocks
Triggers
I/O
JTAG
etc.
ADC data
ADC data
Fig. 4.3 Testbench for top-level design. Grey boxes only included when doing simulation of daisy
chaining. Double box on SAMPA indicates a wrapper for emulating some of the analogue behaviour
The behavioural model for the SAMPA contains separate processes for modelling
of the clock generator, the event generator, the reset generator, and the 32 channels
including filtering, compression, and memory handling. Modelling of the channel
pipeline is cycle-accurate and in phase with the pipeline in the SAMPA so that
debugging of issues can be easily done by comparing the data in the pipeline between
the model and the real code. The behavioural model tries to emulate the memories of
the SAMPA as close as possible so that it takes into account overflows. The memories
and its pointers are accessible from the checker through use of shared variables.
The data generators can be set up to generate different sequences of signals
depending on what is to be tested. It can produce full range sawtooth waves, which
aids in debugging since it makes it easier to compare the output data of the model
and the real circuitry when an issue occurs and determine if something happened too
early or too late and by how many cycles. It can also be set up to run with random
input data, which by adjusting the zero suppression threshold of the filters can easily
emulate different data occupancies for verification of buffers and serial links. Additionally, it can read plain CSV files with sample data or custom data files from for
instance TPC physics runs in 2010, which has both normal data as well as what is
101
Test
sequencer
SAMPA 1
SAMPA 2
11x Checker
Checker
32x Data
generators
32x Data
generators
Behavioural
model
Behavioural
model
Daisy chain
link
11x serial links
Slow control
Clocks
Triggers
I/O
JTAG
etc.
ADC data
ADC data
Fig. 4.3 Testbench for top-level design. Grey boxes only included when doing simulation of daisy
chaining. Double box on SAMPA indicates a wrapper for emulating some of the analogue behaviour
The behavioural model for the SAMPA contains separate processes for modelling
of the clock generator, the event generator, the reset generator, and the 32 channels
including filtering, compression, and memory handling. Modelling of the channel
pipeline is cycle-accurate and in phase with the pipeline in the SAMPA so that
debugging of issues can be easily done by comparing the data in the pipeline between
the model and the real code. The behavioural model tries to emulate the memories of
the SAMPA as close as possible so that it takes into account overflows. The memories
and its pointers are accessible from the checker through use of shared variables.
The data generators can be set up to generate different sequences of signals
depending on what is to be tested. It can produce full range sawtooth waves, which
aids in debugging since it makes it easier to compare the output data of the model
and the real circuitry when an issue occurs and determine if something happened too
early or too late and by how many cycles. It can also be set up to run with random
input data, which by adjusting the zero suppression threshold of the filters can easily
emulate different data occupancies for verification of buffers and serial links. Additionally, it can read plain CSV files with sample data or custom data files from for
instance TPC physics runs in 2010, which has both normal data as well as what is