88
3 SAMPA Chip Implementation
corrected after it is read out from the memory and if a double error is found the state
machine resets its memory pointers to the start of the current packet that is being
prepared on the write side. A parity bit of the payload is also included in the header,
providing a way to determine for the readout system if there has been an upset in the
payload data.
Due to space concerns, the design does not use any EDAC techniques on a per
address basis for the memories as this would require one or more extra bits per
address, increasing the design by 10% for a parity bit, 40% for Hamming(14,10) or
50% for SECDED with Hamming(15,10). A parity bit would only be of benefit if
the specific data could be marked as bad and excluded from further processing. This
would only be practical to do for the payload memory, but would require that the
extra parity bit per payload word be transmitted along with the payload, significantly
increasing the bandwidth needed.
The time-based subtraction memories (pedestal memories) and the memories used
for the pre-trigger delay do not have any form of built-in mitigation added. Since
the pre-trigger memory is essentially an extension of the sample data-path, which is
also not protected, an error in this memory is of no great concern, as it will only alter
the value of a single sample. An upset in the pedestal memory would, however, be
persistent and of greater concern. Like for the data memories, there is no protection
included here either due to limited device area. A technique to mitigate upsets in the
pedestal memories is to refresh the content between data taking runs, or whenever
an opportunity becomes available, where the memory is not in use.
3.5 Design for Low Power
Power consumption in a CMOS device consists of dynamic power when the logic
is transitioning and leakage power when the logic is in a non-switching static mode.
The leakage power is mainly dependent on the manufacturing process and the supply
voltage. As the digital and analogue have separate power domains, it is possible to
lower the digital supply voltage if a power reduction is needed. This would come at
the cost of lowering the maximum operational speed and lowering the noise margin.
Timing verification has been done to verify that the device operates correctly in
the worst-case characterization corner, which has the voltage at 1.08 V. An option
would have been to have several power domains in the digital design that could
be independently powered down, but this would likely negatively affect the power
routing, which possibly would lead to an increase in noise.
Dynamic power is due to switching of capacitances and the short circuits that
occurs from supply to ground when transitioning from one output level to another.
The switching power is proportional to α f CV dd
2 , where α is the activity factor
i.e. the fraction of the circuit that is switching, f is the clock frequency, C is the
node capacitance and V dd is the supply voltage. Therefore, the dynamic power can be
lowered by reducing the operational clock frequency, preventing logic from switching
3 SAMPA Chip Implementation
corrected after it is read out from the memory and if a double error is found the state
machine resets its memory pointers to the start of the current packet that is being
prepared on the write side. A parity bit of the payload is also included in the header,
providing a way to determine for the readout system if there has been an upset in the
payload data.
Due to space concerns, the design does not use any EDAC techniques on a per
address basis for the memories as this would require one or more extra bits per
address, increasing the design by 10% for a parity bit, 40% for Hamming(14,10) or
50% for SECDED with Hamming(15,10). A parity bit would only be of benefit if
the specific data could be marked as bad and excluded from further processing. This
would only be practical to do for the payload memory, but would require that the
extra parity bit per payload word be transmitted along with the payload, significantly
increasing the bandwidth needed.
The time-based subtraction memories (pedestal memories) and the memories used
for the pre-trigger delay do not have any form of built-in mitigation added. Since
the pre-trigger memory is essentially an extension of the sample data-path, which is
also not protected, an error in this memory is of no great concern, as it will only alter
the value of a single sample. An upset in the pedestal memory would, however, be
persistent and of greater concern. Like for the data memories, there is no protection
included here either due to limited device area. A technique to mitigate upsets in the
pedestal memories is to refresh the content between data taking runs, or whenever
an opportunity becomes available, where the memory is not in use.
3.5 Design for Low Power
Power consumption in a CMOS device consists of dynamic power when the logic
is transitioning and leakage power when the logic is in a non-switching static mode.
The leakage power is mainly dependent on the manufacturing process and the supply
voltage. As the digital and analogue have separate power domains, it is possible to
lower the digital supply voltage if a power reduction is needed. This would come at
the cost of lowering the maximum operational speed and lowering the noise margin.
Timing verification has been done to verify that the device operates correctly in
the worst-case characterization corner, which has the voltage at 1.08 V. An option
would have been to have several power domains in the digital design that could
be independently powered down, but this would likely negatively affect the power
routing, which possibly would lead to an increase in noise.
Dynamic power is due to switching of capacitances and the short circuits that
occurs from supply to ground when transitioning from one output level to another.
The switching power is proportional to α f CV dd
2 , where α is the activity factor
i.e. the fraction of the circuit that is switching, f is the clock frequency, C is the
node capacitance and V dd is the supply voltage. Therefore, the dynamic power can be
lowered by reducing the operational clock frequency, preventing logic from switching