3.3 Design for Test
83
3.3.5 Miscellaneous Test Features
Some other test features have been implemented to aid in the verification of parts
of the design. A multiplexer is inserted before the output of serial link 0, which can
output signals from internal circuitry, or from any of the inputs, depending on the
setting of a configuration register. The signal from the either of the three trigger
inputs can, for instance, be set up in loopback mode and routed back out. This can
be used for determining round-trip delay of the system in a production environment.
For instance, if the device that receives the data from the SAMPA is located far away,
there could be a significant propagation delay of the data due to the length of the
optical fibres or wires. By configuring the device in this loop-back mode, sending a
pulse to one of the trigger ports and counting the cycles until a pulse is received back
will enable a coarse time estimate to be determined. This loop-back mode can also
be used for qualification the SLVS driver/receiver pair with the help of an external
Bit Error Rate Tester (BERT).
The daisy chain data input can also be routed directly out so that the complete
device can be bypassed when it is used in a daisy chain mode. This can be beneficial in
case a device stops operating properly, but the data from the second device can still be
used. The signal can also be tapped after the controllable input-delay compensation
chain for the daisy chain data input, so that the actual delay can be measured.
A Pseudo Random Binary Sequence (PRBS) generator has been designed for
easy qualification of the SLVS driver independently of the receiver. The sequence
is generated from a 31-bit maximum length Linear Feedback Shift Register (LFSR)
that feeds back the XNOR of output 31 and 28. The generator runs on the serial link
clock for maximum speed.
A simple ADC serializer can be set up to serialize a single channel for test purposes. Selection of the channel is done by changing a configuration register (SERCHSEL). A 6-bit preamble (b010011) is sent MSB first and the sample data follows.
The samples are serialized with the serial link half clock so that running with a main
clock of 320 MHz and an ADC clock of 10 MHz there will be a total of 16 bits sent.
The internally generated clocks from the clock divider circuitry can be output to
verify jitter and frequency stability. As the clock divider supplies a delayed clock
to the digital design in relation to the clock that goes to the ADCs, it is possible to
compare the intrinsic delay between the clocks and to quantify the delay for each
step configuration of the programmable delay chain.
The clock generated from the ring oscillator described in Sect. 3.3.4 can be output
to determine more accurately the frequency, or to view the waveform on an oscilloscope. The oscillation is only active after the ring oscillator test has been enabled,
and then only for 256 ADC clock cycles or 512 oscillator cycles, whichever is the
shortest. It should oscillate at about 100 MHz in the worst-case corner, 220 MHz for
the best case and 160 MHz for the typical case, based on simulation and available
propagation delay values from the manufacturer’s datasheet.
83
3.3.5 Miscellaneous Test Features
Some other test features have been implemented to aid in the verification of parts
of the design. A multiplexer is inserted before the output of serial link 0, which can
output signals from internal circuitry, or from any of the inputs, depending on the
setting of a configuration register. The signal from the either of the three trigger
inputs can, for instance, be set up in loopback mode and routed back out. This can
be used for determining round-trip delay of the system in a production environment.
For instance, if the device that receives the data from the SAMPA is located far away,
there could be a significant propagation delay of the data due to the length of the
optical fibres or wires. By configuring the device in this loop-back mode, sending a
pulse to one of the trigger ports and counting the cycles until a pulse is received back
will enable a coarse time estimate to be determined. This loop-back mode can also
be used for qualification the SLVS driver/receiver pair with the help of an external
Bit Error Rate Tester (BERT).
The daisy chain data input can also be routed directly out so that the complete
device can be bypassed when it is used in a daisy chain mode. This can be beneficial in
case a device stops operating properly, but the data from the second device can still be
used. The signal can also be tapped after the controllable input-delay compensation
chain for the daisy chain data input, so that the actual delay can be measured.
A Pseudo Random Binary Sequence (PRBS) generator has been designed for
easy qualification of the SLVS driver independently of the receiver. The sequence
is generated from a 31-bit maximum length Linear Feedback Shift Register (LFSR)
that feeds back the XNOR of output 31 and 28. The generator runs on the serial link
clock for maximum speed.
A simple ADC serializer can be set up to serialize a single channel for test purposes. Selection of the channel is done by changing a configuration register (SERCHSEL). A 6-bit preamble (b010011) is sent MSB first and the sample data follows.
The samples are serialized with the serial link half clock so that running with a main
clock of 320 MHz and an ADC clock of 10 MHz there will be a total of 16 bits sent.
The internally generated clocks from the clock divider circuitry can be output to
verify jitter and frequency stability. As the clock divider supplies a delayed clock
to the digital design in relation to the clock that goes to the ADCs, it is possible to
compare the intrinsic delay between the clocks and to quantify the delay for each
step configuration of the programmable delay chain.
The clock generated from the ring oscillator described in Sect. 3.3.4 can be output
to determine more accurately the frequency, or to view the waveform on an oscilloscope. The oscillation is only active after the ring oscillator test has been enabled,
and then only for 256 ADC clock cycles or 512 oscillator cycles, whichever is the
shortest. It should oscillate at about 100 MHz in the worst-case corner, 220 MHz for
the best case and 160 MHz for the typical case, based on simulation and available
propagation delay values from the manufacturer’s datasheet.