7.8 Methods for Controlling Safety …
721
operations described above. The author demonstrates that building such locks by
manipulating finite states and performed compilations during implementation of
hardware IC synthesis taking into account the unique PUF state is actually a means
of implementing a program that is effectively meshed for the intruder and described
by the random events model [118]. Even though various similar heuristic methods
for FSM meshing had been suggested earlier, e.g., in [120, 137], finite guarantee of
reliability had not been ensured there for such building. However, the value of the
suggested method and the proof of its reliability for building a meshed FSM go far
beyond the limits of the hardware metering method applied to ICs and considered
here and extend to other spheres, including the works performed to hide confidential
information and mesh sequential circuits [120, 137]. Detailed description and proof
of effectiveness of this method go beyond the goals of our book. In order to make
sure that the suggested method will actually be failsafe with regard to the spectrum
of suggested attacks, the readers can address the source [126] themselves.
Another interesting method of internal hardware metering that is also based
on FSM modifications was suggested in [94]. However, this method is drastically
different from the one described above due to the fact that it suggests adding only
a few states. However, the microcircuit in this case is supplemented with a great
number of transistors (implemented by combinational logic) so that all state transitions become functions of unique uncloneable chip identifiers. It is interesting to
note that this hardware metering method can also be applied if the developer uses
third-party IP blocks, where it is possible to open access, block or otherwise control
each IP core on chip only with the permission of the owner.
7.8.6 External Active Hardware Metering of Microcircuits
External Active IC metering methods allow the developer to interlock each IC using
the so-called asymmetric cryptography, which requires the use of a specific external
key. The use of asymmetrical cryptography for external IC measurements was first
suggested in the EPIC method [134]. Since EPIC serves as a basis for most subsequent
works dedicated to external active hardware metering, and we have already mentioned
it, we are going to briefly examine this methodology here.
In order to maintain the PKC method (Public Key Cryptography) known to specialists, the holder of IP right shall generate a pair of monitoring keys (public and private)
instead of one; this pair will remain unchanged throughout the lifecycle of the microcircuit. The private monitoring key (MK-Pri) includes IP rights only for this specific
microcircuit design and is never transferred to another party. Each chip manufactured
according to this method generates its own public and private key pairs during initial
activation (IC power-up). There are also the public monitoring key (MK-Pub) and
the minimal logic circuit for support of the combinational EPIC locking mechanism
on the register transmission level.
EPIC implements the combinational interlock in main modules of the chip by
adding XOR gates to several non-critical connecting conductors selected on the
721
operations described above. The author demonstrates that building such locks by
manipulating finite states and performed compilations during implementation of
hardware IC synthesis taking into account the unique PUF state is actually a means
of implementing a program that is effectively meshed for the intruder and described
by the random events model [118]. Even though various similar heuristic methods
for FSM meshing had been suggested earlier, e.g., in [120, 137], finite guarantee of
reliability had not been ensured there for such building. However, the value of the
suggested method and the proof of its reliability for building a meshed FSM go far
beyond the limits of the hardware metering method applied to ICs and considered
here and extend to other spheres, including the works performed to hide confidential
information and mesh sequential circuits [120, 137]. Detailed description and proof
of effectiveness of this method go beyond the goals of our book. In order to make
sure that the suggested method will actually be failsafe with regard to the spectrum
of suggested attacks, the readers can address the source [126] themselves.
Another interesting method of internal hardware metering that is also based
on FSM modifications was suggested in [94]. However, this method is drastically
different from the one described above due to the fact that it suggests adding only
a few states. However, the microcircuit in this case is supplemented with a great
number of transistors (implemented by combinational logic) so that all state transitions become functions of unique uncloneable chip identifiers. It is interesting to
note that this hardware metering method can also be applied if the developer uses
third-party IP blocks, where it is possible to open access, block or otherwise control
each IP core on chip only with the permission of the owner.
7.8.6 External Active Hardware Metering of Microcircuits
External Active IC metering methods allow the developer to interlock each IC using
the so-called asymmetric cryptography, which requires the use of a specific external
key. The use of asymmetrical cryptography for external IC measurements was first
suggested in the EPIC method [134]. Since EPIC serves as a basis for most subsequent
works dedicated to external active hardware metering, and we have already mentioned
it, we are going to briefly examine this methodology here.
In order to maintain the PKC method (Public Key Cryptography) known to specialists, the holder of IP right shall generate a pair of monitoring keys (public and private)
instead of one; this pair will remain unchanged throughout the lifecycle of the microcircuit. The private monitoring key (MK-Pri) includes IP rights only for this specific
microcircuit design and is never transferred to another party. Each chip manufactured
according to this method generates its own public and private key pairs during initial
activation (IC power-up). There are also the public monitoring key (MK-Pub) and
the minimal logic circuit for support of the combinational EPIC locking mechanism
on the register transmission level.
EPIC implements the combinational interlock in main modules of the chip by
adding XOR gates to several non-critical connecting conductors selected on the