7.8 Methods for Controlling Safety …
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and legal subject that can calculate the enabling sequence for each of such original
disabled chips. Such experience developer can additionally calculate the so-called
error correction code (ECC) to prevent any possible changes for these uncloneable
digital identifiers. It needs to be said that this ECC code is extremely important for
security, since certain bits of the PUF response can sometimes be unstable and change
at a certain time after sending the relevant test signals due to various noises, changes
in the environmental conditions (e.g., temperature or radiation) or due to structural
instability of the circuit. Keys for ECC and chip unlocking shall be sent back to the
manufacturer after performance of the necessary procedures.
A number of papers [94, 97] also discuss such interesting methods that can use
additional significant information provided by the manufacturer of the microcircuit
about components of its design, including features of operation of locking/unlocking
circuits in the real time and the possibility of continuous (not based on request)
authentication for additional control purposes.
7.8.5 Intrinsic (Integrated) Active Hardware Measurements
of Microcircuits
Historically, intrinsic metering [97] was the first family of practically implemented
hardware metering. In this class of works, the active IC control mechanism uses:
(1) functional design description, (2) unique and uncloneable IC identifiers. All the
necessary interlocks are embedded within the design of a regular digital microcircuit
model in the form of a finite state machine (FSM). The developer uses the source
description of the project on the high level in order to generate a project behavior
model in the FSM format. FSM is usually represented by an STG (state transition
graph), where the points of the graph correspond to states in the FSM, while the
transitions between FSM states are represented by directional edges adjacent to the
points. In the following, we use the terms FSM and STG interchangeably. Let us
consider the method described in [97] in more detail. Here, the source FSM of
the project before its further modification is used. Since it has |S states, hardware
implementation of the original can be performed using K = log |S triggers.
After that, the developer modifies the FSM, increasing the number of its
states and transitions. The authors call the modified design a boosted finite state
machine (BFSM). In order to built such BFSM with |S
| +|S, K
= log{|S
| +|S|}
triggers will be required. Moreover, additional edges are introduced in the BSFM
in order to ensure accessibility of its additional states. It should be noted that for
linear growth in the number of triggers designated as K = K
—K, the number of
states increase exponentially. Actually, by adding a certain number of triggers, it is
possible to set S » S so that the number of entered new states is exponentially much
higher than |S|.
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and legal subject that can calculate the enabling sequence for each of such original
disabled chips. Such experience developer can additionally calculate the so-called
error correction code (ECC) to prevent any possible changes for these uncloneable
digital identifiers. It needs to be said that this ECC code is extremely important for
security, since certain bits of the PUF response can sometimes be unstable and change
at a certain time after sending the relevant test signals due to various noises, changes
in the environmental conditions (e.g., temperature or radiation) or due to structural
instability of the circuit. Keys for ECC and chip unlocking shall be sent back to the
manufacturer after performance of the necessary procedures.
A number of papers [94, 97] also discuss such interesting methods that can use
additional significant information provided by the manufacturer of the microcircuit
about components of its design, including features of operation of locking/unlocking
circuits in the real time and the possibility of continuous (not based on request)
authentication for additional control purposes.
7.8.5 Intrinsic (Integrated) Active Hardware Measurements
of Microcircuits
Historically, intrinsic metering [97] was the first family of practically implemented
hardware metering. In this class of works, the active IC control mechanism uses:
(1) functional design description, (2) unique and uncloneable IC identifiers. All the
necessary interlocks are embedded within the design of a regular digital microcircuit
model in the form of a finite state machine (FSM). The developer uses the source
description of the project on the high level in order to generate a project behavior
model in the FSM format. FSM is usually represented by an STG (state transition
graph), where the points of the graph correspond to states in the FSM, while the
transitions between FSM states are represented by directional edges adjacent to the
points. In the following, we use the terms FSM and STG interchangeably. Let us
consider the method described in [97] in more detail. Here, the source FSM of
the project before its further modification is used. Since it has |S states, hardware
implementation of the original can be performed using K = log |S triggers.
After that, the developer modifies the FSM, increasing the number of its
states and transitions. The authors call the modified design a boosted finite state
machine (BFSM). In order to built such BFSM with |S
| +|S, K
= log{|S
| +|S|}
triggers will be required. Moreover, additional edges are introduced in the BSFM
in order to ensure accessibility of its additional states. It should be noted that for
linear growth in the number of triggers designated as K = K
—K, the number of
states increase exponentially. Actually, by adding a certain number of triggers, it is
possible to set S » S so that the number of entered new states is exponentially much
higher than |S|.