714
7 Countermeasures Against Hardware Trojans
design files. The solutions suggested in [128, 129] suggested using chip designs that
needed to have a single digital data transmission path, which shall be controlled by
several different specification versions instead of just one version. In this case, a
small portion of such modernized chip is preserved programmable so that all control
chains are programmed in the chip only after its production in silicon.
Another design method for implementation of several such control paths for each
data channel was suggested in [128, 129]. For example, one elegant solution to this
problem is rearranging the subset of variables assigned to each specific internal IC
register in a certain manner. In order to achieve such multiplicity during the stage
of logic synthesis, reserve equivalent states are created for the set of possible states
selected by the IC developer. The selection shall be based on the existing technical
restrictions on various possible competitive states, which shall be preserved in the
regions of storage of separate variables in order to keep hardware costs of internal
registers on a very low level. In this approach, each copy of a variable will be
assigned a different state, while any artificial rearrangement from the range of similar
assignments can be used by the IC developer for separate equivalent states. Since
state attribution is usually implemented by simple coloring of a graph, creation of
such backup states corresponds only to adding a necessary point to the graph and
replicating all edges of the node replicated for this new point. State can be assigned
to such modified graph by using standard SAD means. Programmable read logic in
such registers makes it possible to quickly select the necessary correct rearrangement
of variables for each copy.
The protocol of implementation of passive hardware metering methods to detect
unresolved chips consists in tracking and assessing uniqueness of the analyzed chips.
Right before testing a potentially unresolved chip, the programmable part with indication of specific rearrangements of control circuits is uploaded to the testing system.
After that, if more than one copy of a separate unauthorized rearrangement is detected
during testing, the operator is automatically notified of the fake component. This
protocol will work properly if a sufficient number of chips are in direct access mode,
and if they can be requested and supplied by the manufacturer based on their rearrangement variant. One of the methods of implementation of real-time requests is
the so-called XORing the states of the FFs or execution of other methods of system
parity verification.
We should note one of interesting scenarios of implementation of such passive
metering when the chips are returned to the developer in programmed state, and the
developer directly inputs controller specifications before testing the chips. One of
the conditions for implementation of this method is that each legal owner of IP rights
for the microcircuit shall ensure that each chip is programmed in a unique manner,
and that serial chip production is in no way involved in such programming operation
or even knows about this process. However, this approach in itself will not deter the
attackers very much, since any intruder having access to these chips can theoretically
copy the contents of this programmed memory and use this information to configure
other similar chips. It should be noted that this paper also proves the technical possibility of integration of such programmable components with any uncloneable IDs
embedded in the design of such protected chip that uses even the most basic logic
7 Countermeasures Against Hardware Trojans
design files. The solutions suggested in [128, 129] suggested using chip designs that
needed to have a single digital data transmission path, which shall be controlled by
several different specification versions instead of just one version. In this case, a
small portion of such modernized chip is preserved programmable so that all control
chains are programmed in the chip only after its production in silicon.
Another design method for implementation of several such control paths for each
data channel was suggested in [128, 129]. For example, one elegant solution to this
problem is rearranging the subset of variables assigned to each specific internal IC
register in a certain manner. In order to achieve such multiplicity during the stage
of logic synthesis, reserve equivalent states are created for the set of possible states
selected by the IC developer. The selection shall be based on the existing technical
restrictions on various possible competitive states, which shall be preserved in the
regions of storage of separate variables in order to keep hardware costs of internal
registers on a very low level. In this approach, each copy of a variable will be
assigned a different state, while any artificial rearrangement from the range of similar
assignments can be used by the IC developer for separate equivalent states. Since
state attribution is usually implemented by simple coloring of a graph, creation of
such backup states corresponds only to adding a necessary point to the graph and
replicating all edges of the node replicated for this new point. State can be assigned
to such modified graph by using standard SAD means. Programmable read logic in
such registers makes it possible to quickly select the necessary correct rearrangement
of variables for each copy.
The protocol of implementation of passive hardware metering methods to detect
unresolved chips consists in tracking and assessing uniqueness of the analyzed chips.
Right before testing a potentially unresolved chip, the programmable part with indication of specific rearrangements of control circuits is uploaded to the testing system.
After that, if more than one copy of a separate unauthorized rearrangement is detected
during testing, the operator is automatically notified of the fake component. This
protocol will work properly if a sufficient number of chips are in direct access mode,
and if they can be requested and supplied by the manufacturer based on their rearrangement variant. One of the methods of implementation of real-time requests is
the so-called XORing the states of the FFs or execution of other methods of system
parity verification.
We should note one of interesting scenarios of implementation of such passive
metering when the chips are returned to the developer in programmed state, and the
developer directly inputs controller specifications before testing the chips. One of
the conditions for implementation of this method is that each legal owner of IP rights
for the microcircuit shall ensure that each chip is programmed in a unique manner,
and that serial chip production is in no way involved in such programming operation
or even knows about this process. However, this approach in itself will not deter the
attackers very much, since any intruder having access to these chips can theoretically
copy the contents of this programmed memory and use this information to configure
other similar chips. It should be noted that this paper also proves the technical possibility of integration of such programmable components with any uncloneable IDs
embedded in the design of such protected chip that uses even the most basic logic