706
7 Countermeasures Against Hardware Trojans
Fig. 7.21 Block diagram of an example of development with implementation of protection of
FPGA projects from copying [97]
Fig. 7.22 Authentication block structure (SHA-1 IFF Engine) [97]
In this example, the user project is a regular 8-bit binary counter with permission
input. Using this design reference as a template, the user can simply replace this
counter with user’s own project.
In addition to the user project, FPGA contains the authentication block implementing the IFF verification (SHA-1 IFF Engine). The structure of this block is
shown in Fig. 7.22.
Authentication block consists of three modules:
• RNG_8bits.vhd—8-bit random number generator;
• small_micro_32.vhd—module calculating MAC of the generated array of random
numbers in accordance with the SHA-1 algorithm and comparing it to the MAC
read from the special memory microcircuit DS28E01;
• One_Wire.vhd is the module implementing single-wire interface between FPGA
and the DS28E01 microcircuit.
The block has the following input/output ports:
• Clock_In—clock input;
• Resetn_In—input asynchronous signal of reset/restart;
• One_Wire—bidirectional signal for data exchange via single-wire interface with
the DS28E01 microcircuit;
• Enable—output signal that enables or disables operation of a user project.
The user can set the following parameters:
7 Countermeasures Against Hardware Trojans
Fig. 7.21 Block diagram of an example of development with implementation of protection of
FPGA projects from copying [97]
Fig. 7.22 Authentication block structure (SHA-1 IFF Engine) [97]
In this example, the user project is a regular 8-bit binary counter with permission
input. Using this design reference as a template, the user can simply replace this
counter with user’s own project.
In addition to the user project, FPGA contains the authentication block implementing the IFF verification (SHA-1 IFF Engine). The structure of this block is
shown in Fig. 7.22.
Authentication block consists of three modules:
• RNG_8bits.vhd—8-bit random number generator;
• small_micro_32.vhd—module calculating MAC of the generated array of random
numbers in accordance with the SHA-1 algorithm and comparing it to the MAC
read from the special memory microcircuit DS28E01;
• One_Wire.vhd is the module implementing single-wire interface between FPGA
and the DS28E01 microcircuit.
The block has the following input/output ports:
• Clock_In—clock input;
• Resetn_In—input asynchronous signal of reset/restart;
• One_Wire—bidirectional signal for data exchange via single-wire interface with
the DS28E01 microcircuit;
• Enable—output signal that enables or disables operation of a user project.
The user can set the following parameters: