7.7 Software and Hardware Methods of Protecting …
705
FPGA
d — Reset
System
synchronization
Unlocking
User design
Fig. 7.20 Principle of implementation of the IFF concept
recorded in the EEPROM data area. MAC is calculated using the 64-bit key saved
in the secret EEPROM field of the DS28E01 microcircuit.
Additional protection of the project can be provided by checking the identification
number, which is unique for each DS28E01 microcircuit.
Single-wire (1-Wire) interface is implemented in the DS28E01 microcircuit [115];
therefore, only one I/O line is required to connect this mircocircuit to FPGA.
According to the 1-Wire specification, this I/O line of the FPGA shall be bidirectional, and its output stage shall be a buffer with an open drain. In order to ensure
a level of the logical unit, the line is pulled up by an external resistor to the power
supply voltage of the corresponding I/O bank.
7.7.2 Reference Design Microcircuit Series by Altera
The Altera company suggests a reference design where the IFF concept is
used to protect projects in Cyclone III FPGA from unauthorized copying (CIII_
Design_Security_Enabler project). Figure 7.21 shows the block diagram of this
reference design.