684
7 Countermeasures Against Hardware Trojans
Requirements
Requirements>Specification
Tests>Specification
Implementation>Specification
Change log
Technical
specifications
System
developers and
engineers
Change log
Testing
engineers
Test data set
Components,
module, process,
line, n-m
Components,
module, process,
line, n-m
Change log
Block
List of connections
Gate
Fig. 7.15 Traceability in microcircuit design process suggested in [72]
hierarchy or transformed according to the technology are optimized regardless of
boundaries of modules. Depending on the target platform, output synthesis data can
be individual gates or reference tables (in FPGA). The optimizer shall unite these
reference tags of the source code: e.g., labels for merged elements accumulate in
the resulting element. However, input signal of a fully remote individual element
is usually replaced by static connection with a logic 0 or 1 as input data for the
following element. If the latter, this input inherits the labels, not the global logic 0 or
1 source. In other cases, such as entirely removed address bus lines accompanied by
resized or removed address decoders, collecting all labels doesn’t seem so helpful
and needs some balance.
Saving such metadata on external semiconductor production units poses certain
additional difficulties. For example, standardized extension for GDSII files (graphic
database system files) is required, since GDSII is in fact an industrial standard for
IC topology data.
It should be noted that this method of continuous traceability from requirements to
the source code for each separate transistor is extremely useful during implementation
of certain debugging tasks, and not only in our specific example described below.
7 Countermeasures Against Hardware Trojans
Requirements
Requirements>Specification
Tests>Specification
Implementation>Specification
Change log
Technical
specifications
System
developers and
engineers
Change log
Testing
engineers
Test data set
Components,
module, process,
line, n-m
Components,
module, process,
line, n-m
Change log
Block
List of connections
Gate
Fig. 7.15 Traceability in microcircuit design process suggested in [72]
hierarchy or transformed according to the technology are optimized regardless of
boundaries of modules. Depending on the target platform, output synthesis data can
be individual gates or reference tables (in FPGA). The optimizer shall unite these
reference tags of the source code: e.g., labels for merged elements accumulate in
the resulting element. However, input signal of a fully remote individual element
is usually replaced by static connection with a logic 0 or 1 as input data for the
following element. If the latter, this input inherits the labels, not the global logic 0 or
1 source. In other cases, such as entirely removed address bus lines accompanied by
resized or removed address decoders, collecting all labels doesn’t seem so helpful
and needs some balance.
Saving such metadata on external semiconductor production units poses certain
additional difficulties. For example, standardized extension for GDSII files (graphic
database system files) is required, since GDSII is in fact an industrial standard for
IC topology data.
It should be noted that this method of continuous traceability from requirements to
the source code for each separate transistor is extremely useful during implementation
of certain debugging tasks, and not only in our specific example described below.