7.4 Using Classic Methods of Reliable …
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consist of gates and their connecting conductors. The verification mechanism tests
the design for compliance with specification requirements after equal intervals. This
is also a route stage during which testing and modeling are performed.
After performing the synthesis stage, the created netlist is tested for compliance
with the implementation conceived by the developer, using the equivalence check.
The disclosed netlist is further topologically implemented for a specific production
technology and saved in the GDSII format. At this point, testing schemes are introduced, which support detection of possible errors (not necessarily Trojans) in the
product during the subsequent phases. For a developer without production facilities,
this is the last stage performed within the firm. The stage of tapeout marks transferring the IC design to external contractors. The production plant (maskshop) provides
lithographic masks for production of chips. First, entire wafers are tested; after that,
separate ICs are tested. However, even developers with access to a park of production
equipment ditch some of the stages due to economy reasons or due to the fact that
certain stages are best performed by narrow and experienced contractors.
7.4.3 Possible Attack Types
According to the classification presented in [72], attackers are divided into four
general groups based on the development phase they are active in, i.e., design
attackers, synthesis attackers, fabrication attackers, and distribution attackers [75]. In
Fig. 7.13, these attacker types are visualized in relation to the hardware development
phases they are active in and Fig. 7.14 provides an overview of treats.
A design attacker is active up to the implementation phase where it has full access
to design files as well as source code. This access is obtained by organizing a regular
hacker attack or with the help of an insider attacker with legitimate access rights.
Such an attacker is able to add or remove circuit elements or otherwise intrude the
IC structure for implementation of future attacks.
Synthesis attackers compromise computer-aided design (CAD) tools or scripts
running them, which output a modified representation without modifying the source
code. Such attacks are extremely difficult to detect due to the fact that they are
included in synthesis software. Thereby the attacker is able to add Trojan logic,
mangle critical logic, metering IPs or circuits, or steal the respective information.
A fabrication attacker unfolds his/her activities after tapeout and is typically
external to the IC designer. The attackers are able to add/remove any components by
modifying the geometrical topology pattern, reverse engineering or IC metering.
The fourth group, the distribution attackers, sell counterfeit products with modified
circuitry.
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consist of gates and their connecting conductors. The verification mechanism tests
the design for compliance with specification requirements after equal intervals. This
is also a route stage during which testing and modeling are performed.
After performing the synthesis stage, the created netlist is tested for compliance
with the implementation conceived by the developer, using the equivalence check.
The disclosed netlist is further topologically implemented for a specific production
technology and saved in the GDSII format. At this point, testing schemes are introduced, which support detection of possible errors (not necessarily Trojans) in the
product during the subsequent phases. For a developer without production facilities,
this is the last stage performed within the firm. The stage of tapeout marks transferring the IC design to external contractors. The production plant (maskshop) provides
lithographic masks for production of chips. First, entire wafers are tested; after that,
separate ICs are tested. However, even developers with access to a park of production
equipment ditch some of the stages due to economy reasons or due to the fact that
certain stages are best performed by narrow and experienced contractors.
7.4.3 Possible Attack Types
According to the classification presented in [72], attackers are divided into four
general groups based on the development phase they are active in, i.e., design
attackers, synthesis attackers, fabrication attackers, and distribution attackers [75]. In
Fig. 7.13, these attacker types are visualized in relation to the hardware development
phases they are active in and Fig. 7.14 provides an overview of treats.
A design attacker is active up to the implementation phase where it has full access
to design files as well as source code. This access is obtained by organizing a regular
hacker attack or with the help of an insider attacker with legitimate access rights.
Such an attacker is able to add or remove circuit elements or otherwise intrude the
IC structure for implementation of future attacks.
Synthesis attackers compromise computer-aided design (CAD) tools or scripts
running them, which output a modified representation without modifying the source
code. Such attacks are extremely difficult to detect due to the fact that they are
included in synthesis software. Thereby the attacker is able to add Trojan logic,
mangle critical logic, metering IPs or circuits, or steal the respective information.
A fabrication attacker unfolds his/her activities after tapeout and is typically
external to the IC designer. The attackers are able to add/remove any components by
modifying the geometrical topology pattern, reverse engineering or IC metering.
The fourth group, the distribution attackers, sell counterfeit products with modified
circuitry.