7.3 Using the IEEE Std. 1500 Standard in Order …
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M-FSM in IDLE and disabling all output signals. IIPS RSTN and WRSTN together
define four operating modes of the SoC:
(1) {IIPS_RSTN, WRSTN} = “0”, functional mode;
(2) {IIPS_RSTN, WRSTN} = “1”, basic SoC testing mode;
(3) {IIPS_RSTN, WRSTN} =«11» , advanced SoC test mode requiring active core
scan chain for quick testing of a delay;
(4) {IIPS_RSTN, WRSTN} = “0”, IIPS security mode.
In mode (1) and (2), IIPS is not turned on. Hence mode (2) can only perform
basic SoC testing where core scan chains are disabled, and delay-fault testing is
not supported. Mode (3) enables IIPS to allow scan-chain-based SoC testing and
delay-fault testing. One requirement in this procedure is that IIPS should not have
unnecessary (redundant) state transitions in order to avoid interfering with the normal
testing procedure. For example, in scan-based testing, IIPS should enable the scan
chains as requested and then stay idle during the rest of the test. If M-FSM happens to
enter ScanPUF or TrojDet state, the test clock WRCK and scan shift signal ShiftWR
will be tampered, causing wrong test responses. Similarly, during delay testing, IIPS
should transition to the TrojDet state to provide the appropriate clock signal without
subsequent state transition. To achieve such“functional locking,” states SCLOCK and
TDLOCK are added to M-FSM for scan-based and delay testing, respectively. In the
locking states, proper output signals are retained, but any state transition is disallowed
except for resetting the entire IIPS to IDLE with IIPS_RSTN. In particular, in the SC
LOCK state, IIPS maintains the scan chain enable signals as determined in SC_EN
state. Similarly, the clock and test control signals in TrojDet state are available in
TD_LOCK state for quick SoC delay testing.
7.3.5 Design of IIPS Security Functions
It should be noted that scan chains are the most popular feature of DfT in modern
ICs. They serve as the main means of post-production control and standard testing
of ICs due to their capability to ensure wide test coverage using a relatively simple
structure. Scan chain also facilitates development and support of hardware support
of microcircuits by means of connecting to the JTAG interface to identify a possible
hardware Trojan embedded in the circuit [66]. Scan chains, however, are doubleedged swords in terms of security of hardware, such as cryptographic processors
or ASICs. Additional control and monitoring abilities ensured by scan chains can
also help a highly qualified intruder to obtain secret internal information (e.g., a
cryptographic key) or intermediate data. Earlier studies [67] demonstrated that by
using AES in functional and scanning modes in sequence, it is possible to observe
intermediate calculations of each period of clock pulses through the scan chain. In
case of an attack with an open text, secret key can be easily detected.
Several safe scan architectures have been suggested to prevent access of unauthorized users to scan chains. The main principle of the majority of these methods
673
M-FSM in IDLE and disabling all output signals. IIPS RSTN and WRSTN together
define four operating modes of the SoC:
(1) {IIPS_RSTN, WRSTN} = “0”, functional mode;
(2) {IIPS_RSTN, WRSTN} = “1”, basic SoC testing mode;
(3) {IIPS_RSTN, WRSTN} =«11» , advanced SoC test mode requiring active core
scan chain for quick testing of a delay;
(4) {IIPS_RSTN, WRSTN} = “0”, IIPS security mode.
In mode (1) and (2), IIPS is not turned on. Hence mode (2) can only perform
basic SoC testing where core scan chains are disabled, and delay-fault testing is
not supported. Mode (3) enables IIPS to allow scan-chain-based SoC testing and
delay-fault testing. One requirement in this procedure is that IIPS should not have
unnecessary (redundant) state transitions in order to avoid interfering with the normal
testing procedure. For example, in scan-based testing, IIPS should enable the scan
chains as requested and then stay idle during the rest of the test. If M-FSM happens to
enter ScanPUF or TrojDet state, the test clock WRCK and scan shift signal ShiftWR
will be tampered, causing wrong test responses. Similarly, during delay testing, IIPS
should transition to the TrojDet state to provide the appropriate clock signal without
subsequent state transition. To achieve such“functional locking,” states SCLOCK and
TDLOCK are added to M-FSM for scan-based and delay testing, respectively. In the
locking states, proper output signals are retained, but any state transition is disallowed
except for resetting the entire IIPS to IDLE with IIPS_RSTN. In particular, in the SC
LOCK state, IIPS maintains the scan chain enable signals as determined in SC_EN
state. Similarly, the clock and test control signals in TrojDet state are available in
TD_LOCK state for quick SoC delay testing.
7.3.5 Design of IIPS Security Functions
It should be noted that scan chains are the most popular feature of DfT in modern
ICs. They serve as the main means of post-production control and standard testing
of ICs due to their capability to ensure wide test coverage using a relatively simple
structure. Scan chain also facilitates development and support of hardware support
of microcircuits by means of connecting to the JTAG interface to identify a possible
hardware Trojan embedded in the circuit [66]. Scan chains, however, are doubleedged swords in terms of security of hardware, such as cryptographic processors
or ASICs. Additional control and monitoring abilities ensured by scan chains can
also help a highly qualified intruder to obtain secret internal information (e.g., a
cryptographic key) or intermediate data. Earlier studies [67] demonstrated that by
using AES in functional and scanning modes in sequence, it is possible to observe
intermediate calculations of each period of clock pulses through the scan chain. In
case of an attack with an open text, secret key can be easily detected.
Several safe scan architectures have been suggested to prevent access of unauthorized users to scan chains. The main principle of the majority of these methods