664
7 Countermeasures Against Hardware Trojans
Figure 7.6 shows simplified structure of the protected bus suggested in the paper
[29]. In a normally operating system, this bus structure permits connection between
corresponding elements of the master and slave devices in accordance with the signals
received from the arbiter and decoder, data passage traffic, specific addresses and
status of each transaction. Such protected bus matrix detects, block, and reports any
malicious waiting signals from a Trojan (infected) slave device.
When a slave device needs additional time to complete a data read or write operation set by the master device, it can generate an additional waiting signal in order
for the master device to know that the operation will be soon completed.
For example, if the system bus operates at 200 MHz, and the access to memory is
synchronized at 50 MHz, the memory controller can add a waiting signal for at least
for synchronization signals, during which the master device needs to read something
from memory or write something in memory. Microcircuit built into the system and
infected with a hardware Trojan can use a waiting signal to stop the system, thus
forcing the master device to wait for an unlimited time and keeping the arbiter from
switching the status on the bus.
Fig. 7.6 Safe organization of the structure of SoC bus matrix [29]
7 Countermeasures Against Hardware Trojans
Figure 7.6 shows simplified structure of the protected bus suggested in the paper
[29]. In a normally operating system, this bus structure permits connection between
corresponding elements of the master and slave devices in accordance with the signals
received from the arbiter and decoder, data passage traffic, specific addresses and
status of each transaction. Such protected bus matrix detects, block, and reports any
malicious waiting signals from a Trojan (infected) slave device.
When a slave device needs additional time to complete a data read or write operation set by the master device, it can generate an additional waiting signal in order
for the master device to know that the operation will be soon completed.
For example, if the system bus operates at 200 MHz, and the access to memory is
synchronized at 50 MHz, the memory controller can add a waiting signal for at least
for synchronization signals, during which the master device needs to read something
from memory or write something in memory. Microcircuit built into the system and
infected with a hardware Trojan can use a waiting signal to stop the system, thus
forcing the master device to wait for an unlimited time and keeping the arbiter from
switching the status on the bus.
Fig. 7.6 Safe organization of the structure of SoC bus matrix [29]