7.2 A Trojan-Resistant System …
661
Available address
register
Identifier register
Latch enable
Latch enable
Standard address
matrix
Comparator
Limited address start
register
End register
Register of a template
malicious slave device
Detection
HSEL of the quick-action
selection channel
Fig. 7.3 Structural diagram of a protected address decoder for a system on chip of the malicious
slave device
in order for the future attempts by the intruders to obtain the status of the master bus
node to be properly processed.
This protected address decoder can also effectively block the access performed
by standard master devices to the malicious slave devices that are already known
to the CPU. Of course, this malicious slave device can attempt to stop operation at
the bus by setting the standard mode of continuous waiting. However, this operation
mode can be detected using the bus matrix block and the obtained information about
the specific number of a slave device, which will be automatically recorded in the
mask register of the slave Trojan devices. The value of the (mask of) the slave Trojan
device automatically blocks connection of the system bus to the slave device in which
the hardware Trojan has been activated. When the master device finally attempts to
access this malicious slave device, address decoder automatically redirects access
to another slave device set by the user and containing specially reserved ranges of
empty addresses, thus effectively excluding the slave Trojan device block from the
SoC system bus.
7.2.4 Structure and Operation Principle of the Arbiter Block
The so-called arbiter is usually used to ensure that the bust is accessed by only one
master device. Such arbiter performs observations and simultaneously has the status
of the master node of the bus. This exact device decides which of the requesters has
the highest priority and provides status only to this master device at a given specific
661
Available address
register
Identifier register
Latch enable
Latch enable
Standard address
matrix
Comparator
Limited address start
register
End register
Register of a template
malicious slave device
Detection
HSEL of the quick-action
selection channel
Fig. 7.3 Structural diagram of a protected address decoder for a system on chip of the malicious
slave device
in order for the future attempts by the intruders to obtain the status of the master bus
node to be properly processed.
This protected address decoder can also effectively block the access performed
by standard master devices to the malicious slave devices that are already known
to the CPU. Of course, this malicious slave device can attempt to stop operation at
the bus by setting the standard mode of continuous waiting. However, this operation
mode can be detected using the bus matrix block and the obtained information about
the specific number of a slave device, which will be automatically recorded in the
mask register of the slave Trojan devices. The value of the (mask of) the slave Trojan
device automatically blocks connection of the system bus to the slave device in which
the hardware Trojan has been activated. When the master device finally attempts to
access this malicious slave device, address decoder automatically redirects access
to another slave device set by the user and containing specially reserved ranges of
empty addresses, thus effectively excluding the slave Trojan device block from the
SoC system bus.
7.2.4 Structure and Operation Principle of the Arbiter Block
The so-called arbiter is usually used to ensure that the bust is accessed by only one
master device. Such arbiter performs observations and simultaneously has the status
of the master node of the bus. This exact device decides which of the requesters has
the highest priority and provides status only to this master device at a given specific