652
7 Countermeasures Against Hardware Trojans
blocks performing self-testing of ICs and detection of such embedded hardware
Trojans. Such additional logic known as design-for-enabling-security (DEFENSE)
is integrated in SoC to perform real-time safety checks by multiplexing different parts
of the system using a special checker. For example, legitimacy of access and states,
situations associated with DoS mistakes and system safety can be checked. If an attack
is detected in real time, countermeasures are taken automatically, e.g., all suspicious
logic blocks are immediately disabled. The authors also suggest using additional
known methods, such as failsafe states, backup logic blocks, and copying the current
state in case of detection of an attack. Providing complex coverage of various options
of hardware attacks in real-time mode is a fairly difficult task; therefore, there is still
no effective prototype of the DEFENSE platform. Today, an equally difficult task is
on the table performing such countermeasures in real-time mode without interrupting
the IC operation.
The authors of [16] suggest measuring the unique checksum of the hardware
over a certain very limited period of time using special trusted analytical equipment.
Such hardware checksum is calculated for all low-level micro-architecture processor
elements involved in operations. Hardware is periodically polled, and the checksum
is defined for a limited time.
The authors suppose that the actual checksum cannot be emulated or imitated
within such short time, and only authentic hardware means can provide a correct
response over this time. This mechanism guarantees absence of hardware Trojans
introduced after IC production. In order to ensure such control known as microarchitecture signature function (MSF) and generate unique response to the request, the
researchers have developed new instructions for the processor. However, as it turned
out in practice, such approach doesn’t make it possible to detect Trojans implemented
into the project during specification, topology design, verification, or production.
A special “heartbeat” function was suggested in [8] to counter threats from hardware Trojans related to DoS attacks by checking continuous operation of the IC.
In this case, non-cacheable samples from memory are added to the software, after
which these signals appear on the memory bus as periodic yet random intervals, the
occurrence of which is used to raise the question to the security service—whether
the IC has been subjected to a DoS attack.
7.1.3 Reconfigurable Architectures
The use of various modifications of reconfigurable logic to counter hardware Trojans
has a number of significant advantages, but also poses new challenges and problems
for IC developers. As we know, there is a whole range of various reconfigurable logic
devices, including
• FPGA—chips with high logical density, where most of the device area is
reprogrammable;
7 Countermeasures Against Hardware Trojans
blocks performing self-testing of ICs and detection of such embedded hardware
Trojans. Such additional logic known as design-for-enabling-security (DEFENSE)
is integrated in SoC to perform real-time safety checks by multiplexing different parts
of the system using a special checker. For example, legitimacy of access and states,
situations associated with DoS mistakes and system safety can be checked. If an attack
is detected in real time, countermeasures are taken automatically, e.g., all suspicious
logic blocks are immediately disabled. The authors also suggest using additional
known methods, such as failsafe states, backup logic blocks, and copying the current
state in case of detection of an attack. Providing complex coverage of various options
of hardware attacks in real-time mode is a fairly difficult task; therefore, there is still
no effective prototype of the DEFENSE platform. Today, an equally difficult task is
on the table performing such countermeasures in real-time mode without interrupting
the IC operation.
The authors of [16] suggest measuring the unique checksum of the hardware
over a certain very limited period of time using special trusted analytical equipment.
Such hardware checksum is calculated for all low-level micro-architecture processor
elements involved in operations. Hardware is periodically polled, and the checksum
is defined for a limited time.
The authors suppose that the actual checksum cannot be emulated or imitated
within such short time, and only authentic hardware means can provide a correct
response over this time. This mechanism guarantees absence of hardware Trojans
introduced after IC production. In order to ensure such control known as microarchitecture signature function (MSF) and generate unique response to the request, the
researchers have developed new instructions for the processor. However, as it turned
out in practice, such approach doesn’t make it possible to detect Trojans implemented
into the project during specification, topology design, verification, or production.
A special “heartbeat” function was suggested in [8] to counter threats from hardware Trojans related to DoS attacks by checking continuous operation of the IC.
In this case, non-cacheable samples from memory are added to the software, after
which these signals appear on the memory bus as periodic yet random intervals, the
occurrence of which is used to raise the question to the security service—whether
the IC has been subjected to a DoS attack.
7.1.3 Reconfigurable Architectures
The use of various modifications of reconfigurable logic to counter hardware Trojans
has a number of significant advantages, but also poses new challenges and problems
for IC developers. As we know, there is a whole range of various reconfigurable logic
devices, including
• FPGA—chips with high logical density, where most of the device area is
reprogrammable;