7.1 Hardware and Software Methods …
651
The authors of [11] developed this idea by introducing the concept of Silicon
Security Harness. The proposed concept includes several protection levels that are
ensured by hardware means and system components or implemented as a part of the
general IC architecture. It is aimed at ensuring protective measures and increasing
resistance to the effect of hardware Trojans introduced into the system.
7.1.2 Protected Architectures on the RTL Level
Implementation of special modifications in the IC architecture was offered in a
number of published works as a method of protection from already introduced hardware Trojans. This approach is based on adding (or altering) basic logic gates of the
microcircuit for identification of presence or notification of activation of hardware
Trojans.
For example, the work [12] examines complex firmware for countering hardware
Trojans, which is known as BlueChip. This defence strategy includes using various
security components during both design and operation of an electronic systems in
order to counter hardware Trojans with random localization at the RTL level. The
untrusted circuit identification (UCI) algorithm developed by the authors of [11]
and the set of corresponding instrumental means automatically identify and exclude
potentially dangerous circuits at the RTL level for processor ICs. During project
verification, all suspicious circuits that have been included in the project but do not
affect states of any outputs during testing are detected and deleted. These deleted
hardware devices are replaced with the exception-causing logic (the so-called logic
of unexpected logic) if the deleted fragment is ever activated. This can happen due to
potential activation of a Trojan or provision of unauthorized access to the system initiated by such remote fragment. Low-level software by means of emulation attempts
to recover and predict possible effects that could be caused by action of such detected
suspicious areas.
It is necessary to note an important detail: the BlueChip concept was actually
tested on the processor (Aeroflex Caisler AB) designed on the Xilinx Virtex5 FPGA.
As demonstrated in work [13], this processor is basic for many types of NASA and
European Space Agency spacecrafts. The security concept here is mostly ensured
by trusted software components and only partially trusted hardware means used to
emulate deleted fragments. In order to extend this approach to the general case of
IC designing, it is possible to use a trusted coprocessor, which will help to identify
possible exceptions and perform corresponding emulation during deletion of incorrect hardware devices. BlueChip concept also requires improvement, since there are
already various hardware implementations [14] that are not detected by the UCI
algorithm and successfully passes standard verification.
In this regard, it should be noted that there are currently no mechanisms for
protection from Trojans ensuring their detection before operation of ICs in actual
devices. The authors of [15] suggest performing detection of attacks associated with
presence of Trojans in ICs only during operation by using additional integrated logic
651
The authors of [11] developed this idea by introducing the concept of Silicon
Security Harness. The proposed concept includes several protection levels that are
ensured by hardware means and system components or implemented as a part of the
general IC architecture. It is aimed at ensuring protective measures and increasing
resistance to the effect of hardware Trojans introduced into the system.
7.1.2 Protected Architectures on the RTL Level
Implementation of special modifications in the IC architecture was offered in a
number of published works as a method of protection from already introduced hardware Trojans. This approach is based on adding (or altering) basic logic gates of the
microcircuit for identification of presence or notification of activation of hardware
Trojans.
For example, the work [12] examines complex firmware for countering hardware
Trojans, which is known as BlueChip. This defence strategy includes using various
security components during both design and operation of an electronic systems in
order to counter hardware Trojans with random localization at the RTL level. The
untrusted circuit identification (UCI) algorithm developed by the authors of [11]
and the set of corresponding instrumental means automatically identify and exclude
potentially dangerous circuits at the RTL level for processor ICs. During project
verification, all suspicious circuits that have been included in the project but do not
affect states of any outputs during testing are detected and deleted. These deleted
hardware devices are replaced with the exception-causing logic (the so-called logic
of unexpected logic) if the deleted fragment is ever activated. This can happen due to
potential activation of a Trojan or provision of unauthorized access to the system initiated by such remote fragment. Low-level software by means of emulation attempts
to recover and predict possible effects that could be caused by action of such detected
suspicious areas.
It is necessary to note an important detail: the BlueChip concept was actually
tested on the processor (Aeroflex Caisler AB) designed on the Xilinx Virtex5 FPGA.
As demonstrated in work [13], this processor is basic for many types of NASA and
European Space Agency spacecrafts. The security concept here is mostly ensured
by trusted software components and only partially trusted hardware means used to
emulate deleted fragments. In order to extend this approach to the general case of
IC designing, it is possible to use a trusted coprocessor, which will help to identify
possible exceptions and perform corresponding emulation during deletion of incorrect hardware devices. BlueChip concept also requires improvement, since there are
already various hardware implementations [14] that are not detected by the UCI
algorithm and successfully passes standard verification.
In this regard, it should be noted that there are currently no mechanisms for
protection from Trojans ensuring their detection before operation of ICs in actual
devices. The authors of [15] suggest performing detection of attacks associated with
presence of Trojans in ICs only during operation by using additional integrated logic