596
6 Reverse Engineering of Microcircuits
– Creating element library for tracing and setting all necessary parameters;
– Circuit tracing and recovery of electrical connections;
– Detection of tracing errors;
– Transferring the circuit to the programs of electrical signal passing simulation.
Creating element libraries makes it possible to partially or even completely automate the process of recovery of an electrical circuit. The use of recognition library
during recovery of basic electrical circuits makes it possible to significantly reduce
the required time and perform the process in parallel due to performance of topology
and circuitry elements by several specialists. During the operation of the system,
its training is basically performed, which increases the effectiveness of automated
image analysis.
6.6 Methods of Preparing Samples of Submicron
Microcircuits to Be Studied Using Electrophysical SEM
Methods
6.6.1 Development of Methods for Preparing Samples
of Submicron Microcircuits to Study These Samples
Using SEM
There are multiple methods of preparing samples to be studied on a scanning
electronic microscope. The subjects of interest in microelectronics are IC surface
or cleavage [10]. For example, when analyzing IC surface, linear dimensions of
topology elements (gate width, metal buses, separations), quality of their application, etc., are measured. Moreover, analysis of the IC surface makes it possible to
identify design rule of the product and (in case of presence of test elements) determine
the extent to which the manufactured circuit conforms to the requirements. Analysis of the vertical structure makes it possible analyze the vertical topology of the
chip—the thickness of metals, interlayer dielectrics, polycrystalline silicon. Vertical
structure is used to determine causes of IC failures as well as stages of production
during which they were formed. In other words, vertical topology of a product makes
it possible to control the quality of the IC production process. Thus, there are the
following methods of preparing samples for SEM depending on the task.
When analyzing surface of the product:
– Fastening of the image on a special conductive adhesive tape or a holder with the
face up. Instead of the adhesive tape, it is possible to use a special conductive
glue;
– Production of thin sections of the product surface.
During analysis of the vertical topology of the product:
6 Reverse Engineering of Microcircuits
– Creating element library for tracing and setting all necessary parameters;
– Circuit tracing and recovery of electrical connections;
– Detection of tracing errors;
– Transferring the circuit to the programs of electrical signal passing simulation.
Creating element libraries makes it possible to partially or even completely automate the process of recovery of an electrical circuit. The use of recognition library
during recovery of basic electrical circuits makes it possible to significantly reduce
the required time and perform the process in parallel due to performance of topology
and circuitry elements by several specialists. During the operation of the system,
its training is basically performed, which increases the effectiveness of automated
image analysis.
6.6 Methods of Preparing Samples of Submicron
Microcircuits to Be Studied Using Electrophysical SEM
Methods
6.6.1 Development of Methods for Preparing Samples
of Submicron Microcircuits to Study These Samples
Using SEM
There are multiple methods of preparing samples to be studied on a scanning
electronic microscope. The subjects of interest in microelectronics are IC surface
or cleavage [10]. For example, when analyzing IC surface, linear dimensions of
topology elements (gate width, metal buses, separations), quality of their application, etc., are measured. Moreover, analysis of the IC surface makes it possible to
identify design rule of the product and (in case of presence of test elements) determine
the extent to which the manufactured circuit conforms to the requirements. Analysis of the vertical structure makes it possible analyze the vertical topology of the
chip—the thickness of metals, interlayer dielectrics, polycrystalline silicon. Vertical
structure is used to determine causes of IC failures as well as stages of production
during which they were formed. In other words, vertical topology of a product makes
it possible to control the quality of the IC production process. Thus, there are the
following methods of preparing samples for SEM depending on the task.
When analyzing surface of the product:
– Fastening of the image on a special conductive adhesive tape or a holder with the
face up. Instead of the adhesive tape, it is possible to use a special conductive
glue;
– Production of thin sections of the product surface.
During analysis of the vertical topology of the product: