566
6 Reverse Engineering of Microcircuits
Fig. 6.41 An example of drawing a brightness curve and assessing the contrast of images
possible to formulate a common rule for high-quality alignment regardless of element
dimensions: the offset of two fragments of a bitmap topology image relative to each
other shall not exceed half of the smallest structure element; otherwise, erroneous
interpretation of the image topology is possible.
This can best be seen on the topology of conductors of a system of interconnects.
The elimination of the above image defects allows further use of these images in
the systems of automated frame-by-frame and layer-by-layer alignment and creates
prerequisites for creation of software means for automation of electrical circuit
recovery based on the bitmap image of its topology.
The results of development of practical techniques for recovery and analysis of
IC chip topology based on frame-by-frame alignment and layering of digital image
fragments can be acquired by various microscopy methods. In the conditions of
transition to nanoscale topological standards limiting the possibility of mechanical
alignment of IC topology fragments, most effective are the above informational and
methodological approaches of the synthesis of the whole image based on software
compensation of the position of frames and layers relative to each other.
6 Reverse Engineering of Microcircuits
Fig. 6.41 An example of drawing a brightness curve and assessing the contrast of images
possible to formulate a common rule for high-quality alignment regardless of element
dimensions: the offset of two fragments of a bitmap topology image relative to each
other shall not exceed half of the smallest structure element; otherwise, erroneous
interpretation of the image topology is possible.
This can best be seen on the topology of conductors of a system of interconnects.
The elimination of the above image defects allows further use of these images in
the systems of automated frame-by-frame and layer-by-layer alignment and creates
prerequisites for creation of software means for automation of electrical circuit
recovery based on the bitmap image of its topology.
The results of development of practical techniques for recovery and analysis of
IC chip topology based on frame-by-frame alignment and layering of digital image
fragments can be acquired by various microscopy methods. In the conditions of
transition to nanoscale topological standards limiting the possibility of mechanical
alignment of IC topology fragments, most effective are the above informational and
methodological approaches of the synthesis of the whole image based on software
compensation of the position of frames and layers relative to each other.