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5 Methods of Detecting Hardware Trojans in Microcircuits
As a demonstration example of using the TeSR method for identification of
sequential hardware Trojans in microcircuits, the authors of [1] modeled a 32-bit
DLX processor circuit (containing about 20,000 logic gates) in the standard HSPICE
program, using the so-called predictive technology model (PTM) for the 70 nm design
standard [57]. Sets of test vectors were designed to fill the command pipeline with
repeated instructions of NOP or ADD type, which leads to their controlled implementation in one step of the conveyor at a time. Many options of implementation of this
processor were considered—both uninfected and infected with malicious inclusions
of Trojans in various blocks of these microcircuits with the only purpose of proving
the existence of a time-independent (but specific process-dependent) profile in each
uninfected IC. In fact, the typical circuit of the hardware Trojan used by researchers
is a regular autonomous 8-bit binary counter (see Fig. 5.6b), which causes the failure
(activates) when the count reaches the maximum value set by the intruder (e.g., after
64 cycles of continuous operation), which is reasonably considered exceeding the
normal (standard) testing time during production final testing of a microcircuit. The
analyzed main parameter of the side channel is the average value of the dynamic
current consumption of the IC in each period of the clock signals.
Here, it is necessary to take into account that due to chaotic changes in the IC
production process parameters, device parameters are also chaotically shifted from
their nominal values. Figure 5.8a shows the classic influence of changes in the process
parameters on the threshold value of a transistor (V T ); moreover, these numeric values
can vary both due to variations inside the chip and due to variations of their mean
values among chips that can have both chaotic (random) and systemic components
[54]. The effect of such variations of process parameters was assessed by the authors
of the work using the Monte Carlo simulation package in HSPICE with ±20%
variations of V T values between chips and the standard deviation of ±10% for the
variation within a single chip (st).
It is clear that such variations can ultimately mask the effect of the inserted hardware Trojan circuit, as can be seen from the observed overlap region in the modeled
distribution of the average value of current consumption in the reference circuit and
the analyzed circuit that definitely contains a hardware Trojan (see Fig. 5.8b). This
overlap is indicative of definitely large-scale circuits with small embedded hardware
Trojans, which complicates the selection of a single threshold value for distinguishing
between infected and non-infected ICs; this can ultimately cause significant errors
related to wrongful classification (incorrect selection of the demarcation level V T ).
In order for all methods of detection of hardware Trojans based on side-channel
analysis to work properly, it is necessary to exclude the effect of these changes in
the parameters of production process and design features. The authors [1] were the
first to notice during the studies that when comparing dynamic current consumption
profile for the same IC exposed to the same effects under equal electrical load but at
different points in time, it is possible to identify and register characteristic temporary
changes of the supply current value of the hardware Trojan (if present in the IC).
This is due to the fact that this recorded trace of the dynamic supply current in
different time intervals of testing consists of two different components: (a) due to the
same component because of (regularly repeated) switches of the circuit states and
5 Methods of Detecting Hardware Trojans in Microcircuits
As a demonstration example of using the TeSR method for identification of
sequential hardware Trojans in microcircuits, the authors of [1] modeled a 32-bit
DLX processor circuit (containing about 20,000 logic gates) in the standard HSPICE
program, using the so-called predictive technology model (PTM) for the 70 nm design
standard [57]. Sets of test vectors were designed to fill the command pipeline with
repeated instructions of NOP or ADD type, which leads to their controlled implementation in one step of the conveyor at a time. Many options of implementation of this
processor were considered—both uninfected and infected with malicious inclusions
of Trojans in various blocks of these microcircuits with the only purpose of proving
the existence of a time-independent (but specific process-dependent) profile in each
uninfected IC. In fact, the typical circuit of the hardware Trojan used by researchers
is a regular autonomous 8-bit binary counter (see Fig. 5.6b), which causes the failure
(activates) when the count reaches the maximum value set by the intruder (e.g., after
64 cycles of continuous operation), which is reasonably considered exceeding the
normal (standard) testing time during production final testing of a microcircuit. The
analyzed main parameter of the side channel is the average value of the dynamic
current consumption of the IC in each period of the clock signals.
Here, it is necessary to take into account that due to chaotic changes in the IC
production process parameters, device parameters are also chaotically shifted from
their nominal values. Figure 5.8a shows the classic influence of changes in the process
parameters on the threshold value of a transistor (V T ); moreover, these numeric values
can vary both due to variations inside the chip and due to variations of their mean
values among chips that can have both chaotic (random) and systemic components
[54]. The effect of such variations of process parameters was assessed by the authors
of the work using the Monte Carlo simulation package in HSPICE with ±20%
variations of V T values between chips and the standard deviation of ±10% for the
variation within a single chip (st).
It is clear that such variations can ultimately mask the effect of the inserted hardware Trojan circuit, as can be seen from the observed overlap region in the modeled
distribution of the average value of current consumption in the reference circuit and
the analyzed circuit that definitely contains a hardware Trojan (see Fig. 5.8b). This
overlap is indicative of definitely large-scale circuits with small embedded hardware
Trojans, which complicates the selection of a single threshold value for distinguishing
between infected and non-infected ICs; this can ultimately cause significant errors
related to wrongful classification (incorrect selection of the demarcation level V T ).
In order for all methods of detection of hardware Trojans based on side-channel
analysis to work properly, it is necessary to exclude the effect of these changes in
the parameters of production process and design features. The authors [1] were the
first to notice during the studies that when comparing dynamic current consumption
profile for the same IC exposed to the same effects under equal electrical load but at
different points in time, it is possible to identify and register characteristic temporary
changes of the supply current value of the hardware Trojan (if present in the IC).
This is due to the fact that this recorded trace of the dynamic supply current in
different time intervals of testing consists of two different components: (a) due to the
same component because of (regularly repeated) switches of the circuit states and