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5 Methods of Detecting Hardware Trojans in Microcircuits
Nevertheless, most methods based on side-channel analysis are characterized by
a fairly low sensitivity due to natural changes in the microcircuit production process
parameters and rely on comparison to the golden reference, which is usually difficult
to obtain.
In [8], a new approach based on identification and analysis of side channels (loopholes) was suggested. The authors named this approach Temporal Self-Referencing
(TESR). The suggested approach makes it possible to exclude the effect of the everpresent spread of process parameters in different chips as well as within a single chip.
This approach also does not require mandatory presence of a reference or golden IC:
Here, an original approach is used, which is based on identification of potential hardware Trojans by comparing the profile of transient (dynamic) current of the chip to
itself measured during a different time interval.
We should note here a number of features related to implementation of the method.
Firstly, they include features of development of the TeSR test kits generation algorithm, which guarantees extended test coverage in the field of detecting a hardware
Trojan; secondly, specific features of developing the TeSR analysis methodology for
effective detection of sequential types of hardware Trojans, on the basis of which it
is possible to offer a new method of microcircuit design taking into account safety
provison (DfS) in order to ensure solving the TeSR task during testing to find hardto-detect hardware Trojans; lastly, it is necessary to perform subsequent TeSR validation on three typical large serial IP cores and verify effectiveness of this approach by
comparing effectiveness of detection of a hardware Trojan with the standard approach
based on calibration process inside the chip. The authors performed experimental
validation on an FPGA platform using the Xilinx Vertex-IIXC2V500 device.
The BTeSR method primarily focuses on identifying sequential hardware Trojans,
which usually pose a greater threat than their combinational “brothers,” since an
intelligent intruder can use several elements storing given states at once in order to
create a complex hardware Trojan with extremely rare trigger conditions. The main
idea underlying this methodology consist in the fact that when a circuit that contains
no hardware Trojan is forced to undergo the same set of state transitions for many
times, the alternating current profile needs to remain constant throughout different
time intervals. However, general current profile in circuits with embedded hardware
Trojans is measured during multiple time segments when performing the same set
of state transitions of the original circuit due to uncorrelated state transitions of the
hardware Trojan.
The TeSR method can be used without process calibration of reference chips,
since it is performed independently for each IC copy. According to the information
available to us, as of the moment of publication of this book, this is the first approach to
hardware Trojan detection based on side-channel analysis which (1) fully eliminates
the effect of production process variation between chips and inside a chip (both
randomly and systematically) and (2) helps avoid using the reference implementation
of the chip.
5 Methods of Detecting Hardware Trojans in Microcircuits
Nevertheless, most methods based on side-channel analysis are characterized by
a fairly low sensitivity due to natural changes in the microcircuit production process
parameters and rely on comparison to the golden reference, which is usually difficult
to obtain.
In [8], a new approach based on identification and analysis of side channels (loopholes) was suggested. The authors named this approach Temporal Self-Referencing
(TESR). The suggested approach makes it possible to exclude the effect of the everpresent spread of process parameters in different chips as well as within a single chip.
This approach also does not require mandatory presence of a reference or golden IC:
Here, an original approach is used, which is based on identification of potential hardware Trojans by comparing the profile of transient (dynamic) current of the chip to
itself measured during a different time interval.
We should note here a number of features related to implementation of the method.
Firstly, they include features of development of the TeSR test kits generation algorithm, which guarantees extended test coverage in the field of detecting a hardware
Trojan; secondly, specific features of developing the TeSR analysis methodology for
effective detection of sequential types of hardware Trojans, on the basis of which it
is possible to offer a new method of microcircuit design taking into account safety
provison (DfS) in order to ensure solving the TeSR task during testing to find hardto-detect hardware Trojans; lastly, it is necessary to perform subsequent TeSR validation on three typical large serial IP cores and verify effectiveness of this approach by
comparing effectiveness of detection of a hardware Trojan with the standard approach
based on calibration process inside the chip. The authors performed experimental
validation on an FPGA platform using the Xilinx Vertex-IIXC2V500 device.
The BTeSR method primarily focuses on identifying sequential hardware Trojans,
which usually pose a greater threat than their combinational “brothers,” since an
intelligent intruder can use several elements storing given states at once in order to
create a complex hardware Trojan with extremely rare trigger conditions. The main
idea underlying this methodology consist in the fact that when a circuit that contains
no hardware Trojan is forced to undergo the same set of state transitions for many
times, the alternating current profile needs to remain constant throughout different
time intervals. However, general current profile in circuits with embedded hardware
Trojans is measured during multiple time segments when performing the same set
of state transitions of the original circuit due to uncorrelated state transitions of the
hardware Trojan.
The TeSR method can be used without process calibration of reference chips,
since it is performed independently for each IC copy. According to the information
available to us, as of the moment of publication of this book, this is the first approach to
hardware Trojan detection based on side-channel analysis which (1) fully eliminates
the effect of production process variation between chips and inside a chip (both
randomly and systematically) and (2) helps avoid using the reference implementation
of the chip.