5.2 Methods of Detecting Hardware Trojans in Microcircuits Based …
473
the HT trigger sequence can always be expressed as a certain Boolean equation and
implemented with the help of standard LUT tables.
Even in very limited laboratory conditions, this approach can allow any
researchers to insert an extremely simple externally triggered HT circuit that takes up
only two processor sections (of 2071 +2). In practice, however, any HT trigger shall
be expected to be bigger. It is necessary to understand that selection of an eight-bit
activation sequence destroys the intention of a hardware Trojan to be transparent,
since such a short sequence can easily be detected by any expert even using simple
logical testing. Therefore, one can expect that the Trojan trigger sequence for practical use designed by an experienced professional intruder will be much longer (e.g.,
about 80 bits), with a negligible probability of being selected randomly. In [1], the
authors decided to implement such 80-bit comparator in the infected circuits they
had proposed. Since the data are always transmitted byte by byte from the reference
FPGA microcircuit to the tested FPGA, such comparator requires only a small finite
state machine to save the results of current comparison monitoring. In this case, we
get the summary size for the HT circuit of 27 processor Sects. (15 for comparators
and 12 for additional logic for the finite state machine). The size of the HT trigger
in this case will amount to just 1.3% of the entire microcircuit volume.
In order to keep the HT very small, the authors of [1] decided not to install any
payload at all. In other words, these infected circuits can not react to activation
sequence at all. The reason behind this decision was largely intuitive: after all, any
payload scheme will ultimately result in an increase in the size of the Trojan and
is likely to elevate the chances of Trojan detection. By implementing a small HT
triggered with minimum changes in the netlists and excluding the HT payload, the
authors of [13] made the HT extremely difficult to detect, thus complicating or
perhaps even eliminating the possibility of Trojan detection using this method.
Six various yet extremely similar versions of Trojan-infected microcircuits were
implemented. Planing of FPGA mircocircuit topologies for each variant is shown in
Fig. 5.2. Gray points are the unused processor sections; blue points are the processor
sections occupied by the golden reference circuit, while the additional Trojan circuit
(27 processor sections and a certain tracing) is shown in red. In the first three circuits,
HTs were placed in empty points along the top side of FPGA structures (HT a: left,
b: center, c: right), while HTs in the last three circuits were placed symmetrically
along the bottom side (HT d: left, HT e: center, HT f: right). In all cases, the program
of the FPGA editor automatically routed input signals from IOB to LUT.
Measurement data collection. The authors of [1] collected multiple sets of experimental results from EM measurements for various examined FPGA designs, i.e., of
the reference circuit itself and the infected circuits (during the training and correspondence selection phases). These measurements were performed during different times
of the day (and deliberately avoided using temperature control in the laboratory) and
with greater or smaller temporary intervals between them. All measurements were
performed using the same station shown in Fig. 7.2.
Each measurement of EM characteristics corresponded to a single cycle of AES
encryption performance. This covered the time window between receipt of the input
data and the transmission of encrypted text of the output data. In other words, it
473
the HT trigger sequence can always be expressed as a certain Boolean equation and
implemented with the help of standard LUT tables.
Even in very limited laboratory conditions, this approach can allow any
researchers to insert an extremely simple externally triggered HT circuit that takes up
only two processor sections (of 2071 +2). In practice, however, any HT trigger shall
be expected to be bigger. It is necessary to understand that selection of an eight-bit
activation sequence destroys the intention of a hardware Trojan to be transparent,
since such a short sequence can easily be detected by any expert even using simple
logical testing. Therefore, one can expect that the Trojan trigger sequence for practical use designed by an experienced professional intruder will be much longer (e.g.,
about 80 bits), with a negligible probability of being selected randomly. In [1], the
authors decided to implement such 80-bit comparator in the infected circuits they
had proposed. Since the data are always transmitted byte by byte from the reference
FPGA microcircuit to the tested FPGA, such comparator requires only a small finite
state machine to save the results of current comparison monitoring. In this case, we
get the summary size for the HT circuit of 27 processor Sects. (15 for comparators
and 12 for additional logic for the finite state machine). The size of the HT trigger
in this case will amount to just 1.3% of the entire microcircuit volume.
In order to keep the HT very small, the authors of [1] decided not to install any
payload at all. In other words, these infected circuits can not react to activation
sequence at all. The reason behind this decision was largely intuitive: after all, any
payload scheme will ultimately result in an increase in the size of the Trojan and
is likely to elevate the chances of Trojan detection. By implementing a small HT
triggered with minimum changes in the netlists and excluding the HT payload, the
authors of [13] made the HT extremely difficult to detect, thus complicating or
perhaps even eliminating the possibility of Trojan detection using this method.
Six various yet extremely similar versions of Trojan-infected microcircuits were
implemented. Planing of FPGA mircocircuit topologies for each variant is shown in
Fig. 5.2. Gray points are the unused processor sections; blue points are the processor
sections occupied by the golden reference circuit, while the additional Trojan circuit
(27 processor sections and a certain tracing) is shown in red. In the first three circuits,
HTs were placed in empty points along the top side of FPGA structures (HT a: left,
b: center, c: right), while HTs in the last three circuits were placed symmetrically
along the bottom side (HT d: left, HT e: center, HT f: right). In all cases, the program
of the FPGA editor automatically routed input signals from IOB to LUT.
Measurement data collection. The authors of [1] collected multiple sets of experimental results from EM measurements for various examined FPGA designs, i.e., of
the reference circuit itself and the infected circuits (during the training and correspondence selection phases). These measurements were performed during different times
of the day (and deliberately avoided using temperature control in the laboratory) and
with greater or smaller temporary intervals between them. All measurements were
performed using the same station shown in Fig. 7.2.
Each measurement of EM characteristics corresponded to a single cycle of AES
encryption performance. This covered the time window between receipt of the input
data and the transmission of encrypted text of the output data. In other words, it