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U.S. Patent 7 195 931 (2004)
55. B. Hill, R. Karmazin, C.T.O. Otero, J. Tse, R. Manohar, A split-foundry asynchronous FPGA.
In Proceedings of the 2013 IEEE Custom Integrated Circuits Conference (CICC 2013) (2013),
pp. 1–4, http://dx.doi.org/10.1109/CICC.2013.6658536
56. J. Rajendran, O. Sinanoglu, R. Karri, Is split manufacturing secure? in Proceedings of the
Design, Automation and Test in Europe Conference and Exhibition (2013), pp. 1259–1264
57. J. Rajendran, Y. Pino, O. Sinanoglu, R. Karri, Logic encryption: a fault analysis perspective,
in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition
(2012), 953–958
58. Chipworks, Intel’s 22-nm tri-gate transistors exposed (2012), http://www.chipworks.com/
blog/technologyblog/2012/04/23/intels-22-nmtri-gate-transistors-exposed/
59. Defense Advanced Research Projects Agency (DARPA), Integrity and reliability of integrated
circuits (IRIS) (2012), http://wwwdarpa.mil/Our_Work/MTO/Programs/Integrity_and_Rel
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62. Degate, http://www.degate.org/documentation/
63. W.M.V Fleet, M.R. Dransfield, Method of recovering a gate-level netlist from a transistorlevel, U.S. Patent 6 190 433 (1998)
64. M. Hansen, H. Yalcin, J. Hayes, Unveiling the ISCAS-85 benchmarks: a case study in reverse
engineering. IEEE Des. Test Comput. 16(3), 72–80 (1999)
65. W. Li, Z. Wasson, S.A. Seshia, Reverse engineering circuits using behavioral pattern mining,
in Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security
and Trust (HOST 2012) (2012), pp. 83–88, http://dx.doi.org/10.1109/HST.2012.6224325
66. P Subramanyan et al., Reverse engineering digital circuits using functional analysis, in
Proceeding of the Design, Automation and Test in Europe Conference and Exhibition (2013),
pp. 1277–1280
67. Syphermedia, Syphermedia library circuit camouflage technology, http://www.smi.tv/soluti
ons.htm
68. J.P Baukus, L.W Chow, R Cocchi, B.J. Wang, Method and apparatus for camouflaging a
standard cell based integrated circuit with micro circuits and post processing, U.S. Patent
2012 0 139 582 (2012)
69. J.P Baukus, L.W Chow, R.P Cocchi, P Ouyang, B.J. Wang, Building block for a secure CMOS
logic cell library, U.S. Patent 8 111 089 (2012)
70. J.P Baukus, L.W Chow, W Clark. Integrated circuits protected against reverse engineering
and method for fabricating the same using an apparent metal contact line terminating on field
oxide, U.S. Patent 2002 0 096 776 (2002). J.P. Baukus, L.W Chow, R.P. Cocchi, P Ouyang,
B.J. Wang, Camouflaging a standard cell based integrated circuit, U.S. Patent 8 151 235 (2012)
71. J. Rajendran, M. Sam, O. Sinanoglu, R. Karri, Security analysis of integrated circuit camouflaging, in Proceedings of the 2013 ACM SIGSAC Conference on Computer & Communications Security (CCS 2013) (ACM, New York, NY, 2013), pp. 709–720, https://doi.org/10.
1145/2508859.2516656
72. J. Rajendran, O. Sinanoglu, R. Karri, VLSI testing based security metric for IC camouflaging,
in Proceedings of IEEE International Test Conference (2013), https://doi.org/10.1109/test.
2013.6651879