286
4 Hardware Trojans in Microcircuits
Fig. 4.7 Main basic possibilities for introduction of hardware implants into integrated Microcircuits
• Fraud: The intruder can illegally forge (clone) or imitate an original component
of the microcircuit as well as the entire structure of the attacked microcircuit.
Figure 4.7 shows the main possible channels of introduction of hardware Trojans
into microcircuits during all stages of creation of the final project, from the R&D
stage to final assembly and testing of the microcircuit.
Figure 4.8 separately shows the possible risks for the case of using the results of
work of hired third-party centers in a project, regardless of whether such third-party
center carries out the entire project or a part of it.
The gradation of the risk of introducing hardware Trojans is presented here. As
you can see, in this case only the used CAD systems and the template manufacturing
stage have the medium level of risk, while the IP blocks, standard cells, and even
models have the highest level of risk. It should be emphasized that Fig. 4.8 reflects the
specific case when the project is implemented using domestic production, where all
technological operations of chip manufacturing and testing designed by a third-party
design center are implemented.
Figure 4.9 shows the risks of using third-party IP blocks, and Fig. 4.10 shows
the typical system-on-chip (SoC) structure, demonstrating the danger of introducing
4 Hardware Trojans in Microcircuits
Fig. 4.7 Main basic possibilities for introduction of hardware implants into integrated Microcircuits
• Fraud: The intruder can illegally forge (clone) or imitate an original component
of the microcircuit as well as the entire structure of the attacked microcircuit.
Figure 4.7 shows the main possible channels of introduction of hardware Trojans
into microcircuits during all stages of creation of the final project, from the R&D
stage to final assembly and testing of the microcircuit.
Figure 4.8 separately shows the possible risks for the case of using the results of
work of hired third-party centers in a project, regardless of whether such third-party
center carries out the entire project or a part of it.
The gradation of the risk of introducing hardware Trojans is presented here. As
you can see, in this case only the used CAD systems and the template manufacturing
stage have the medium level of risk, while the IP blocks, standard cells, and even
models have the highest level of risk. It should be emphasized that Fig. 4.8 reflects the
specific case when the project is implemented using domestic production, where all
technological operations of chip manufacturing and testing designed by a third-party
design center are implemented.
Figure 4.9 shows the risks of using third-party IP blocks, and Fig. 4.10 shows
the typical system-on-chip (SoC) structure, demonstrating the danger of introducing