2 The Smart “Things” in IoT
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to communicate with its slaves. To implement the arbitration process, each device
must constantly monitor SDA and SCL for start and stop conditions to figure out
when the bus is idle/available or busy. By this approach, a master can realize when
another master is active and using the bus, so it can immediately stop its transfer.
SDA and SCL lines are logic high in normal state. Then the master node can
start the communication. To do so, the master produces a start condition and then
specifies the slave device address. If bit 0 of the address byte is designated 0, then
the master will write to the slave. If not, the master realizes that it should read from
the slave. When all data have been read, or written, the master sends the stop signal,
indicating that the bus is now free and available for use by other devices.
I2C sends data in the form of messages and these messages are separated into
two frame types (see Fig. 2.22) [10]:
• Address Frame – Master determines which slave the message is sent to.
• Data Frame – One or more (8-bit data messages) are transferred from the master
to the slave and vice versa.
Each message in I2C consists of one start and one stop condition:
• Start – In this condition, SCL is high and SDA has transmission from high to low.
After a successful start, the bus is busy and other masters cannot use the bus.
• Stop – In this condition, SCL is high and SDA has transmission from low to high.
After a successful stop, the bus is free and other masters can start using the bus.
After the start condition, the first part of any new communication series is always
the address frame. The master sends the 7-bit address of the slave (starting from
most important bit (MSB)) following by a R/W bit. The R/W indicates if the
operation is a write (0) or a read (1). Write means that the master writes to slave
and read means that the master reads from slave. The 9th bit of any data or address
frame is always known as the NACK/ACK bit. When the initial 8 bits of the frame
have been sent by the master, the slave device gains SDA control. If the slave does
not pull the SDA low prior to the 9th clock pulse, it means that the slave did not
receive the message or was not able to parse it; therefore, the message exchange
stops and the master must determine the next step (see Fig. 2.23) [10].
When the address frame has been successfully received by the slave, the actual
data transmission can begin. The master continues to send clock pulses at regular
intervals. Depending on if the R/W designates a read or write operation, the slave or
master publishes data on the SDA. It should be noted that there is no limitation and
Start
7 or 10 bit: address
frame
Read/write
bit
8 bits: data frame
Message
Ack/Nack
bit
8 bits: data frame
Ack/Nack
bit
Stop
Fig. 2.22 The structure of I2C packets
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to communicate with its slaves. To implement the arbitration process, each device
must constantly monitor SDA and SCL for start and stop conditions to figure out
when the bus is idle/available or busy. By this approach, a master can realize when
another master is active and using the bus, so it can immediately stop its transfer.
SDA and SCL lines are logic high in normal state. Then the master node can
start the communication. To do so, the master produces a start condition and then
specifies the slave device address. If bit 0 of the address byte is designated 0, then
the master will write to the slave. If not, the master realizes that it should read from
the slave. When all data have been read, or written, the master sends the stop signal,
indicating that the bus is now free and available for use by other devices.
I2C sends data in the form of messages and these messages are separated into
two frame types (see Fig. 2.22) [10]:
• Address Frame – Master determines which slave the message is sent to.
• Data Frame – One or more (8-bit data messages) are transferred from the master
to the slave and vice versa.
Each message in I2C consists of one start and one stop condition:
• Start – In this condition, SCL is high and SDA has transmission from high to low.
After a successful start, the bus is busy and other masters cannot use the bus.
• Stop – In this condition, SCL is high and SDA has transmission from low to high.
After a successful stop, the bus is free and other masters can start using the bus.
After the start condition, the first part of any new communication series is always
the address frame. The master sends the 7-bit address of the slave (starting from
most important bit (MSB)) following by a R/W bit. The R/W indicates if the
operation is a write (0) or a read (1). Write means that the master writes to slave
and read means that the master reads from slave. The 9th bit of any data or address
frame is always known as the NACK/ACK bit. When the initial 8 bits of the frame
have been sent by the master, the slave device gains SDA control. If the slave does
not pull the SDA low prior to the 9th clock pulse, it means that the slave did not
receive the message or was not able to parse it; therefore, the message exchange
stops and the master must determine the next step (see Fig. 2.23) [10].
When the address frame has been successfully received by the slave, the actual
data transmission can begin. The master continues to send clock pulses at regular
intervals. Depending on if the R/W designates a read or write operation, the slave or
master publishes data on the SDA. It should be noted that there is no limitation and
Start
7 or 10 bit: address
frame
Read/write
bit
8 bits: data frame
Message
Ack/Nack
bit
8 bits: data frame
Ack/Nack
bit
Stop
Fig. 2.22 The structure of I2C packets