460
M. N. Bojnordi and P. Behnam
P
I
Grounnd
Compute
2
Ground
1
b i-1
b i
(a) Compute Majority
(b) Determine I and P
I
M
Vdd
M
P
b i
Fig. 9.24 The main operations of adjacent MISC cells. (a) Compute majority. (b) Determine I
and P
E, M, I
; {E, M, I} can be employed to access R in XNOR; and bitlines from
adjacent cells are used to access low through
I, C, C
.
Computing the Median Inside MISC Array Computing bit-serial median
requires multiple steps, each of which involves selecting cells through bitlines
and wordlines. Figure 9.24 shows the main operations of adjacent MISC cells in a
row. On every iteration, only one cell of each memory row will be processed. First,
P and I are initialized with nonzero binary values to determine if the cell should be
included in computation. This is necessary to ensure that irrelevant data points are
not included in median computation. To compute the majority vote of a bit position
(b i ), bitlines C from columns b i and b i−1 are connected to ground and bitline C of
the bit position b i is connected to Vdd. As shown in Fig. 9.24a, two current paths
are possible between Vdd and ground. One path is established through column b i
based on the content of data bit (1). Another possible path includes the memristive
element (low) of the neighboring column (b i−1 ) that determines the amount of
current pulled from the computed bitline in case of bit propagation (2). These two
paths are controlled by P and I such that only one (or none) of the columns per
every row contributes to the bitline current. Therefore, only three combinations of
the P and I values (i.e., 00, 01, and 10) are used for computation. However, the P
and I values may change during the computation of a row. First, none of the cells
are selected if P I = 00; second, column b i is selected to be included in the majority
computation if P I = 01; and third, column b i−1 contributes to the majority vote
computation if P I = 10. At every step, the majority is computed by measuring
the total current driven through the compute bitline (C) and comparing it with a
threshold.
One difficulty for the in situ bit-serial median computation is propagating the
minority bit within each row. This operation may result in forming long chains of
MISC cells per row, which impacts the area, delay, and power dissipation significantly. The MISC architecture, however, avoids forming long chains by allowing
only 1s to be propagated from b i−1 to b i . Firstly, 1 and 0 are represented with the
low- and high-resistance states, respectively. Secondly, because of the significant
difference between the high- and low-resistance states in RRAM [108], the currents
contributed to the bitline by those memristive cells in high-resistance states can be
M. N. Bojnordi and P. Behnam
P
I
Grounnd
Compute
2
Ground
1
b i-1
b i
(a) Compute Majority
(b) Determine I and P
I
M
Vdd
M
P
b i
Fig. 9.24 The main operations of adjacent MISC cells. (a) Compute majority. (b) Determine I
and P
E, M, I
; {E, M, I} can be employed to access R in XNOR; and bitlines from
adjacent cells are used to access low through
I, C, C
.
Computing the Median Inside MISC Array Computing bit-serial median
requires multiple steps, each of which involves selecting cells through bitlines
and wordlines. Figure 9.24 shows the main operations of adjacent MISC cells in a
row. On every iteration, only one cell of each memory row will be processed. First,
P and I are initialized with nonzero binary values to determine if the cell should be
included in computation. This is necessary to ensure that irrelevant data points are
not included in median computation. To compute the majority vote of a bit position
(b i ), bitlines C from columns b i and b i−1 are connected to ground and bitline C of
the bit position b i is connected to Vdd. As shown in Fig. 9.24a, two current paths
are possible between Vdd and ground. One path is established through column b i
based on the content of data bit (1). Another possible path includes the memristive
element (low) of the neighboring column (b i−1 ) that determines the amount of
current pulled from the computed bitline in case of bit propagation (2). These two
paths are controlled by P and I such that only one (or none) of the columns per
every row contributes to the bitline current. Therefore, only three combinations of
the P and I values (i.e., 00, 01, and 10) are used for computation. However, the P
and I values may change during the computation of a row. First, none of the cells
are selected if P I = 00; second, column b i is selected to be included in the majority
computation if P I = 01; and third, column b i−1 contributes to the majority vote
computation if P I = 10. At every step, the majority is computed by measuring
the total current driven through the compute bitline (C) and comparing it with a
threshold.
One difficulty for the in situ bit-serial median computation is propagating the
minority bit within each row. This operation may result in forming long chains of
MISC cells per row, which impacts the area, delay, and power dissipation significantly. The MISC architecture, however, avoids forming long chains by allowing
only 1s to be propagated from b i−1 to b i . Firstly, 1 and 0 are represented with the
low- and high-resistance states, respectively. Secondly, because of the significant
difference between the high- and low-resistance states in RRAM [108], the currents
contributed to the bitline by those memristive cells in high-resistance states can be