372
W. Chang et al.
h avg =
i=1,2,3
j =1,2,3 E
wc
i (j )
3
< h.
Moreover, the corresponding sensor-to-actuator delay τ sa
i (j ) also varies with cache
reuse as
∀i ∈ {1, 2, 3} ,
τ
sa
i (1) = h i (1) = E
wc
i (1), τ
sa
i (2) = h i (2) = E
wc
i (2), τ
sa
i (3) = E
wc
i (3).
As all control timing parameters have been derived, it can be seen that the
sampling period h i (j) of a control application is non-uniform for the memory-aware
scheme. The average sampling period of S2 is shorter than the uniform sampling
period of S1, due to the WCET reduction resulting from cache reuse. The sensor-toactuator delay τ sa
i (j ) varies. The next task is to develop a controller design method
to exploit the shortened non-uniform sampling periods and achieve better control
performance.
For an application C i with l system states under the conventional memoryoblivious sampling scheme S1, the constant sampling period h is larger than the
constant sensor-to-actuator delay τ sa
i . Therefore, the discrete-time system is
x [k + 1] = A d x [k] + B 1
τ
sa
i
u [k − 1] + B 0
τ
sa
i
u [k] ,
where
B 0
τ
sa
i
=
h−τ sa
i
0
e
At dt × B, B 1
τ
sa
i
=
h
h−τ sa
i
e
At dt × B.
It is assumed that u[−1] = 0 for k = 0. Clearly, the system dynamics depends on
both u[k] and u[k − 1]. Thus, a new system state is defined as
z [k] =
x [k] u [k − 1]
T ,
and the transformed system becomes
z [k + 1] = A S1 z [k] + B S1 u [k] ,
y [k] = C S1 z [k] ,
where