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Fig. 7.6 The general timing model of a control loop
Fig. 7.7 The conventional memory-oblivious sampling order S1
S1 :C 1 (1) −→ C 2 (1) −→ C 3 (1) −→ C 1 (2) −→ C 2 (2) −→
C 3 (2) −→ C 1 (3) −→ C 2 (3) −→ C 3 (3) −→ · · · .
There is no cache reuse in S1 between consecutive executions, considering that
different control applications typically have different instructions to execute. In
other words, when C i (j) starts execution, all instructions of C i need to be brought
into the cache from the flash memory. Therefore,
E
wc
i (1) = E
wc
i (2) = · · · = E
wc
i ,
where E wc
i (j ) is the WCET of the jth execution for C i . The WCET of the
application C i is denoted by E wc
i , since all executions of the same application
have equal WCET. This can be computed with standard WCET analysis techniques,
as discussed before. Clearly, all control applications run with a uniform sampling
period of
h =
i=1,2,3
E
wc
i .
Moreover, for the sensor-to-actuator delay,
τ
sa
i = E
wc
i .
As illustrated in Fig. 7.8, S2 is an example memory-aware sampling order and
summarized as