7 Intelligent and Connected Cyber-Physical Systems: A Perspective. . .
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around the world are able to develop full functionalities of CAVs, as evidenced by
the prototypes and trials, mass production and deployment will not happen if any of
the four issues mentioned above is not sufficiently addressed.
Some recent efforts contributing towards the new methodology are on resourceaware CPS design [1, 2]. That is, the cyber implementation resources are considered
when developing control algorithms directly influencing the physical processes.
This significantly improves the resource dimensioning and utilization and gains
more trust in the system. There are mainly three types of resources: computation,
communication, and memory. Note that the computational resources are often
related to not only the processors, but also the operating systems. The communication resources vary with different protocols. The memory resources are commonly
organized in a hierarchy.
The communication protocols are broadly classified into two groups – eventtriggered (ET) and time-triggered (TT) networks. For instance, the Controller Area
Network (CAN) is ET and has been widely used since its first official release in
1986. FlexRay, standardized in 2013, was designed to be faster and more reliable
than CAN and can be found in many premium cars. Media access control in FlexRay
is based on communication cycles of equal and predefined length in time. Each
communication cycle is divided into a TT static and an optional ET dynamic
segment. Messages can be sent with FlexRay over either the TT or ET segment
using a bandwidth of 10 Mbit/s.
The TT static segment follows a timing division multiple access (TDMA)
policy, where the entire segment is divided into multiple slots with the same
predefined length in time. Each application involved in the TT communication
is assigned a dedicated slot. This allows a predictable temporal behavior. Timesensitive networking (TSN) is currently being developed to provide deterministic
messaging on standard Ethernet. The key features are time synchronization and
traffic scheduling. They are addressed by the 802.1AS and 802.1Qbv standards,
respectively. All participating devices are synchronized to a global time and are
aware of a network schedule that dictates when prioritized messages will be
forwarded from each switch.
The memory resources often have a multi-level hierarchy. For example, the flash
memory has a large size and stores all the application programs and data, but
experiences high read/write latencies (hundreds of processor cycles). The cache (onchip memory in Fig. 7.1) is faster with low read/write latencies (several processor
cycles), but usually limited in size due to its high cost. The access times of cache
and flash memory are denoted as t c and t m , respectively. When a processor executes
an instruction, it checks the cache first. If this instruction is located in the cache,
it is a cache hit and the access time is t c . If this instruction is not in the cache, the
memory block containing it is fetched from the flash memory and then written into
cache. This is a cache miss and the access time is t m . Afterwards, when the same
instruction is called again by the processor, the access time is t c if it is still in the
cache without being replaced. This is a cache reuse.
359
around the world are able to develop full functionalities of CAVs, as evidenced by
the prototypes and trials, mass production and deployment will not happen if any of
the four issues mentioned above is not sufficiently addressed.
Some recent efforts contributing towards the new methodology are on resourceaware CPS design [1, 2]. That is, the cyber implementation resources are considered
when developing control algorithms directly influencing the physical processes.
This significantly improves the resource dimensioning and utilization and gains
more trust in the system. There are mainly three types of resources: computation,
communication, and memory. Note that the computational resources are often
related to not only the processors, but also the operating systems. The communication resources vary with different protocols. The memory resources are commonly
organized in a hierarchy.
The communication protocols are broadly classified into two groups – eventtriggered (ET) and time-triggered (TT) networks. For instance, the Controller Area
Network (CAN) is ET and has been widely used since its first official release in
1986. FlexRay, standardized in 2013, was designed to be faster and more reliable
than CAN and can be found in many premium cars. Media access control in FlexRay
is based on communication cycles of equal and predefined length in time. Each
communication cycle is divided into a TT static and an optional ET dynamic
segment. Messages can be sent with FlexRay over either the TT or ET segment
using a bandwidth of 10 Mbit/s.
The TT static segment follows a timing division multiple access (TDMA)
policy, where the entire segment is divided into multiple slots with the same
predefined length in time. Each application involved in the TT communication
is assigned a dedicated slot. This allows a predictable temporal behavior. Timesensitive networking (TSN) is currently being developed to provide deterministic
messaging on standard Ethernet. The key features are time synchronization and
traffic scheduling. They are addressed by the 802.1AS and 802.1Qbv standards,
respectively. All participating devices are synchronized to a global time and are
aware of a network schedule that dictates when prioritized messages will be
forwarded from each switch.
The memory resources often have a multi-level hierarchy. For example, the flash
memory has a large size and stores all the application programs and data, but
experiences high read/write latencies (hundreds of processor cycles). The cache (onchip memory in Fig. 7.1) is faster with low read/write latencies (several processor
cycles), but usually limited in size due to its high cost. The access times of cache
and flash memory are denoted as t c and t m , respectively. When a processor executes
an instruction, it checks the cache first. If this instruction is located in the cache,
it is a cache hit and the access time is t c . If this instruction is not in the cache, the
memory block containing it is fetched from the flash memory and then written into
cache. This is a cache miss and the access time is t m . Afterwards, when the same
instruction is called again by the processor, the access time is t c if it is still in the
cache without being replaced. This is a cache reuse.