2 The Smart “Things” in IoT
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interrupts disabled in the NVIC as well, if those interrupts are enabled in the
related peripheral control register.
• SLEEPONEXIT – The other way to begin using low-power mode is by enabling
the SLEEPONEXIT bit found in the System Control Register (SCR). When this
bit is designated at 1, it allows the processor to immediately go to low-power
mode once the execution of interrupt/exception is complete, before the program
resumes execution.
The low-power modes enabled on a device are determined by the specific
implementation within the processor family series. The most common low-power
modes in the Cortex-M series include Sleep Mode, Low-Power Run Mode, Stop
Mode, Low-Power Sleep Mode, and Standby Mode.
The main differences between the modes noted above typically can be represented by three important parameters, namely, wake-up time, power consumption,
and performance. The table below compares low-power modes discussed above in
terms of these three parameters. To make this comparison clear, each parameter
uses a ranking scale of #1 to #5 with “#1” being the best possible ranking and “#5”
being the worst. For example, “performance = 1” indicates the highest performance,
and “performance = 5” indicates the worst performance. In general, as power
consumption reduces, performance decreases, and wake-up time increases (see
Table 2.3) [16].
• Low-Power Run Mode – System clock frequency is decreased; however, the core
does not stop.
• Sleep Mode – Only the core stops and all peripherals keep running.
• Low-Power Sleep Mode – A combination of low-power run mode and sleep
mode; core stops and system clock frequency decreases.
• Stop Mode – In this mode, core and external high-speed clocks stop, while
internal clocks and low-speed external clocks work in a limited capacity. This
strategy allows a reduction in the power consumption on the order of nanoamps, while SRAM, registers, as well as a few peripherals remain functional.
For example, UART and I2C can receive data, when it is needed.
• Standby Mode – In this low-power mode, the entire chip stands by. There are
limited options for exiting this mode because only a wake-up pin, a reset signal,
or a real-time clock wake-up event will wake the device. Note that unlike the
other lower power modes, standby mode does not maintain the content of SRAM
and registers. In other words, in the case of wake-up, the whole system will be
reinitialized.
Table 2.3 Low-power modes of Cortex-M based on various parameters
Performance
Power consumption
Wake-up
Low-power run mode
1
5
2
Sleep mode
2
4
1
Low-power sleep mode
3
3
4
Stop mode
4
2
3
Standby mode
5
1
5
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interrupts disabled in the NVIC as well, if those interrupts are enabled in the
related peripheral control register.
• SLEEPONEXIT – The other way to begin using low-power mode is by enabling
the SLEEPONEXIT bit found in the System Control Register (SCR). When this
bit is designated at 1, it allows the processor to immediately go to low-power
mode once the execution of interrupt/exception is complete, before the program
resumes execution.
The low-power modes enabled on a device are determined by the specific
implementation within the processor family series. The most common low-power
modes in the Cortex-M series include Sleep Mode, Low-Power Run Mode, Stop
Mode, Low-Power Sleep Mode, and Standby Mode.
The main differences between the modes noted above typically can be represented by three important parameters, namely, wake-up time, power consumption,
and performance. The table below compares low-power modes discussed above in
terms of these three parameters. To make this comparison clear, each parameter
uses a ranking scale of #1 to #5 with “#1” being the best possible ranking and “#5”
being the worst. For example, “performance = 1” indicates the highest performance,
and “performance = 5” indicates the worst performance. In general, as power
consumption reduces, performance decreases, and wake-up time increases (see
Table 2.3) [16].
• Low-Power Run Mode – System clock frequency is decreased; however, the core
does not stop.
• Sleep Mode – Only the core stops and all peripherals keep running.
• Low-Power Sleep Mode – A combination of low-power run mode and sleep
mode; core stops and system clock frequency decreases.
• Stop Mode – In this mode, core and external high-speed clocks stop, while
internal clocks and low-speed external clocks work in a limited capacity. This
strategy allows a reduction in the power consumption on the order of nanoamps, while SRAM, registers, as well as a few peripherals remain functional.
For example, UART and I2C can receive data, when it is needed.
• Standby Mode – In this low-power mode, the entire chip stands by. There are
limited options for exiting this mode because only a wake-up pin, a reset signal,
or a real-time clock wake-up event will wake the device. Note that unlike the
other lower power modes, standby mode does not maintain the content of SRAM
and registers. In other words, in the case of wake-up, the whole system will be
reinitialized.
Table 2.3 Low-power modes of Cortex-M based on various parameters
Performance
Power consumption
Wake-up
Low-power run mode
1
5
2
Sleep mode
2
4
1
Low-power sleep mode
3
3
4
Stop mode
4
2
3
Standby mode
5
1
5