82
R. Dutta and N. Paitya
Fig. 4 Surface potential variation for SG-PI-TFET under channel length L t = 45 nm with different
gate biases, keeping V DS = 0.5 V
Fig. 5 Electric field profile for SG-PI-TFET under channel length L t = 45 nm, keeping V DS =
0.5 V
R. Dutta and N. Paitya
Fig. 4 Surface potential variation for SG-PI-TFET under channel length L t = 45 nm with different
gate biases, keeping V DS = 0.5 V
Fig. 5 Electric field profile for SG-PI-TFET under channel length L t = 45 nm, keeping V DS =
0.5 V