20.4 Simulator Internal Structure
Main data structure of the interpreter is erric_t, which describes the single virtual
CPU based on ERRIC architecture, with its registers, memory, a status code
describing the current status of the CPU and other auxiliary components, Fig. 20.2.
This structure is passed to most, if not all, functions available in the interpreter
library. Therefore, the functions do not need to store any state regarding the
structure, and thus can be used to simulate multi-core processors by working with
multiple ERRIC CPUs, either asynchronously or by running them in turn.
For more detailed description and explanation on usage of the library, refer to
Appendix 2.
20.5 Interpreter: The Implementation
20.5.1 Design Decisions and Caveats
• The project started with incomplete requirements and lack of full information on
ERRIC architecture (previously called ERA). Because of this, some design
decisions and assumptions may not match the current architecture. In particular,
the RETI instruction is not supported yet.
• The original machine specification utilizes nearly all of the space for instructions, meaning that it is difficult to add additional machine commands.
struct erric_t {
// common registers
lword_t *registers;
// machine memory
word_t *memory;
// size of the memory (in words)
uint32_t memory_size;
// instruction register
word_t IR;
// Status code field, checked after every instruction
sword_t status_code;
};
Fig. 20.2 Main data structure of the interpreter
20.4 Simulator Internal Structure
297
Main data structure of the interpreter is erric_t, which describes the single virtual
CPU based on ERRIC architecture, with its registers, memory, a status code
describing the current status of the CPU and other auxiliary components, Fig. 20.2.
This structure is passed to most, if not all, functions available in the interpreter
library. Therefore, the functions do not need to store any state regarding the
structure, and thus can be used to simulate multi-core processors by working with
multiple ERRIC CPUs, either asynchronously or by running them in turn.
For more detailed description and explanation on usage of the library, refer to
Appendix 2.
20.5 Interpreter: The Implementation
20.5.1 Design Decisions and Caveats
• The project started with incomplete requirements and lack of full information on
ERRIC architecture (previously called ERA). Because of this, some design
decisions and assumptions may not match the current architecture. In particular,
the RETI instruction is not supported yet.
• The original machine specification utilizes nearly all of the space for instructions, meaning that it is difficult to add additional machine commands.
struct erric_t {
// common registers
lword_t *registers;
// machine memory
word_t *memory;
// size of the memory (in words)
uint32_t memory_size;
// instruction register
word_t IR;
// Status code field, checked after every instruction
sword_t status_code;
};
Fig. 20.2 Main data structure of the interpreter
20.4 Simulator Internal Structure
297