The reliability of the ARM [5] is calculated under the assumption that twice the
number of transistors is used in an ARM processor in comparison to ERRIC which
is reflected in the complexity overhead d, which is applied to Eqs. 16.3 and 16.4,
i.e., using d instead of d i and d r .
This estimation is conservative as an ARM processor due to its much more
complex instructions set and implementation (pipelines, cache, etc.) needs probably
more than twice the number of transistors (latest estimation of ARM and ERRIC
complexity enables us to talk about 6:1 [evsy 14]).
It’s obvious that ERRIC has by far the highest MTTF due to its ability to recover
from malfunctions.
Calculating the efficiency of ERRIC and comparing it to ARM are only half the
story. We also should create experiments and provide analytic estimation of the
performance of ERRIC over time. There is no doubt that our next and nearest goal,
in the analysis of evolving process of reliability and performance of resilient
computer system, is to use ERRIC as an example.
16.2 Digging a Bit Deeper in Estimation of Efficiency
of Reliability Solutions
Let us add some more realism for the estimation of efficiency as presented below
(Eq. 16.5):
E ¼
1 þ k
ð
Þ
ð1 þ ckð1 À x bð1ÀxÞ Þ 1 þ x
ð
Þ
ð16:5Þ
Comparing the efficiency of solutions for malfunction tolerance of two processor
models Eq. 16.5 means that if we “kill” malfunctions with coverage c = 1, and
with minimum redundancy (x ! 0), then resulting system will be almost k times
more reliable as all malfunctions are tolerated, and this is reasonable.
In turn, recoverability of hardware requires redundancy, defined for Eq. 16.5 as
b. Clearly, when b is approximately 10–15%—similar to as ERRIC design—the
overall reliability gain is higher, when b ! 1, …, 0.95, the gain decreases
(Fig. 16.3).
Comparing the estimated reliability gain, one can see that the potential of this
architecture is huge, especially and primarily for resilient computer systems.
Additionally, proposed processor is 5–6 smaller in power consumption than
ARM or Intel current models. Therefore, in combination with system software
described in previous chapters, we made a substantial progress in this area on
resilient computer technology and system software.
218
16 ERRIC Reliability
number of transistors is used in an ARM processor in comparison to ERRIC which
is reflected in the complexity overhead d, which is applied to Eqs. 16.3 and 16.4,
i.e., using d instead of d i and d r .
This estimation is conservative as an ARM processor due to its much more
complex instructions set and implementation (pipelines, cache, etc.) needs probably
more than twice the number of transistors (latest estimation of ARM and ERRIC
complexity enables us to talk about 6:1 [evsy 14]).
It’s obvious that ERRIC has by far the highest MTTF due to its ability to recover
from malfunctions.
Calculating the efficiency of ERRIC and comparing it to ARM are only half the
story. We also should create experiments and provide analytic estimation of the
performance of ERRIC over time. There is no doubt that our next and nearest goal,
in the analysis of evolving process of reliability and performance of resilient
computer system, is to use ERRIC as an example.
16.2 Digging a Bit Deeper in Estimation of Efficiency
of Reliability Solutions
Let us add some more realism for the estimation of efficiency as presented below
(Eq. 16.5):
E ¼
1 þ k
ð
Þ
ð1 þ ckð1 À x bð1ÀxÞ Þ 1 þ x
ð
Þ
ð16:5Þ
Comparing the efficiency of solutions for malfunction tolerance of two processor
models Eq. 16.5 means that if we “kill” malfunctions with coverage c = 1, and
with minimum redundancy (x ! 0), then resulting system will be almost k times
more reliable as all malfunctions are tolerated, and this is reasonable.
In turn, recoverability of hardware requires redundancy, defined for Eq. 16.5 as
b. Clearly, when b is approximately 10–15%—similar to as ERRIC design—the
overall reliability gain is higher, when b ! 1, …, 0.95, the gain decreases
(Fig. 16.3).
Comparing the estimated reliability gain, one can see that the potential of this
architecture is huge, especially and primarily for resilient computer systems.
Additionally, proposed processor is 5–6 smaller in power consumption than
ARM or Intel current models. Therefore, in combination with system software
described in previous chapters, we made a substantial progress in this area on
resilient computer technology and system software.
218
16 ERRIC Reliability