Table 14.1 Available instructions
Instr. name Format code Instr. code Opl
Op2
Description
NOP
01
0000
Ignored Ignored Execute no action except increasing
the PC
STOP
00
0000
0
0
Stop instruction execution
TRACE
00
0000
Ri > 0
Rj > 0
Output Ri to debugger. Operandi or
Operand2 must be > 0
RETI
11
0000
Return from interrupt (Address in
ii31)
LD
11
0001
Ri
Rj
Load 32-bit memory at address Ri
into register Rj(Rj: = *Ri)
LDA
11
0010
ignored Rj
Load the value from the next 32-bit
word (rel. to PC) and store it in Rj
{Rj: = constant). Operand 1 is
ignored
ST
11
0011
Ri
Rj
Store content of register Ri to the
memory at address Rj(*Rj: = Ri)
MOV
XX
0100
Ri
Rj
Move content of register Ri to
register Rj(Rj: = Ri)
ADD
XX
0101
Ri
Rj
Arithmetically add the content of Ri
to the content of Rj and store the
result in Rj (Rj: = Rj + Ri)
SUB
XX
0110
Ri
Rj
Arithmetically subtract the content of
Ri to the content of Rj and store the
result in Rj (Rj: = Rj - Ri)
ASR
XX
0111
Ri
Rj
Shift the content of register Ri
arithmetically one bit to the right and
store the result in Rj
ASL
XX
1000
Ri
Rj
Shift the content of register Ri
arithmetically one bit to the left and
store the result in Rj
OR
XX
1001
Ri
Rj
Perform a bitwise logical OR of
register Ri with register Rj and store
the result in Rj
AND
XX
1010
Ri
Rj
Perform a bitwise logical AND of
register Ri with register Rj and store
the result in Rj
XOR
XX
1011
Ri
Rj
Perform a bitwise logical XOR of
register Ri with register Rj and store
the result in Rj
LSL
XX
1100
Ri
Rj
Shift the content of register Ri
logically one bit to the right and store
the result in Rj
LSR
XX
1101
Ri
Rj
Shift the content of register Ri
logically one bit to the left and store
the result in Rj
CND
XX
1110
Ri
Rj
Arithmetic comparison of Ri with Rj
and store the result in Rj
CBR
XX
1111
Ri
Rj
Jump to address in Rj if Ri is non
zero and save PC in Ri
204
14 Hardware: The ERRIC Architecture