14.2 Instruction Set
All the requirements to the processor which are described in (reference) can only be
achieved using an ultra-reduced instruction set, consisting of only 16 instructions
where only two of them are memory instructions (load/store).
This allows to save the state of the processor before each instruction execution,
and, if a fault is detected, to cancel the instruction and re-execute it on the same
processor. Furthermore, such an instruction set generally requires less hardware,
which increases the reliability of a single processor.
The processor has 32 general-purpose registers. They have a width of 32 bits and
are equal, i.e., all registers can be used for every instruction. The instructions are
designed as two register instructions, where the second register is used to store the
result.
The compiler designer has to keep in mind that the content of the second register
is overwritten. Memory access is 32-bit only and has to be aligned to 32-bit.
Every instruction is encoded into 16 bits (see Fig. 14.5). The two highest bits
(bits 14, 15) indicate the format of the operation, which can be 8, 16, or 32 bits.
Not all instructions support a format other than 32 bits, but if they do, they only
use the specified amount of bits in their operand registers and ignore the others.
Bits 10–13 contain the instruction opcode.
Bits 5–9 identify the first operand (register) and bits 0–4 the second operand.
Fig. 14.4 Check generator and checking scheme
202
14 Hardware: The ERRIC Architecture
All the requirements to the processor which are described in (reference) can only be
achieved using an ultra-reduced instruction set, consisting of only 16 instructions
where only two of them are memory instructions (load/store).
This allows to save the state of the processor before each instruction execution,
and, if a fault is detected, to cancel the instruction and re-execute it on the same
processor. Furthermore, such an instruction set generally requires less hardware,
which increases the reliability of a single processor.
The processor has 32 general-purpose registers. They have a width of 32 bits and
are equal, i.e., all registers can be used for every instruction. The instructions are
designed as two register instructions, where the second register is used to store the
result.
The compiler designer has to keep in mind that the content of the second register
is overwritten. Memory access is 32-bit only and has to be aligned to 32-bit.
Every instruction is encoded into 16 bits (see Fig. 14.5). The two highest bits
(bits 14, 15) indicate the format of the operation, which can be 8, 16, or 32 bits.
Not all instructions support a format other than 32 bits, but if they do, they only
use the specified amount of bits in their operand registers and ignore the others.
Bits 10–13 contain the instruction opcode.
Bits 5–9 identify the first operand (register) and bits 0–4 the second operand.
Fig. 14.4 Check generator and checking scheme
202
14 Hardware: The ERRIC Architecture