7.3.4.1 Degradation Phases of a Triplicated System
The most reliable configuration in terms of fault detection and transparent recovery
is triplication. As we have four memory modules available, we use the last one as
spare. The proposed degradation phases of the triplicated system are shown in
Fig. 7.17. Every box represents one possible configuration of the system. The four
numbers in the boxes represent the four memory modules and their current
configuration.
The position in the four numbers identifies the memory module and the value the
memory bank the module is attached to. x stands for failed, and s for spare chip. An
example: 1xx1 means that memory modules number 1 and 4 are connected to bank
1, and the memory modules 2 and 3 are failed or are at least disabled. Bank 1 is
duplicated, as two memory modules are attached to this bank.
By convention, we assume that bank 1 is always in use as ERRIC supports only
absolute addressing. In other words, if code is supposed to run directly from ROM,
all memory addresses must either be absolute or calculated relative to a base address
stored in one of the processor registers, as the addresses cannot be updated in the
ROM. For performance reasons, the former addressing approach is preferable, but
Fig. 7.17 Degradation phases of a triplicated memory system
98
7 Testing, Checking, and Hardware Syndrome
The most reliable configuration in terms of fault detection and transparent recovery
is triplication. As we have four memory modules available, we use the last one as
spare. The proposed degradation phases of the triplicated system are shown in
Fig. 7.17. Every box represents one possible configuration of the system. The four
numbers in the boxes represent the four memory modules and their current
configuration.
The position in the four numbers identifies the memory module and the value the
memory bank the module is attached to. x stands for failed, and s for spare chip. An
example: 1xx1 means that memory modules number 1 and 4 are connected to bank
1, and the memory modules 2 and 3 are failed or are at least disabled. Bank 1 is
duplicated, as two memory modules are attached to this bank.
By convention, we assume that bank 1 is always in use as ERRIC supports only
absolute addressing. In other words, if code is supposed to run directly from ROM,
all memory addresses must either be absolute or calculated relative to a base address
stored in one of the processor registers, as the addresses cannot be updated in the
ROM. For performance reasons, the former addressing approach is preferable, but
Fig. 7.17 Degradation phases of a triplicated memory system
98
7 Testing, Checking, and Hardware Syndrome