7.3.3 Interfacing Zone: The Syndrome as Memory
Configuration Mechanism
Until now we just showed the properties and advantages of such a configurable
memory controller. What we did not explain is how such a controller could be
implemented while still providing interconnection and dynamic exclusion of faulty
components from the operational system.
For this, we suggest to use a so-called T-logic inter-connector, illustrated in
Fig. 7.15, an idealized concept of a hardware switch in the form of a “T” that can
connect or disconnect (for fault containment) from the memory controller by
“rotating”.
This logic is used in the hardware architecture to form a hardware configuration
scheme adjustable to the software or hardware requirements when a hardware
element itself detects faults and thus can’t be involved in further program execution
either on a temporary or permanent basis.
The four T-logic inter-connectors, one per memory module, are physically
contained in the T-logic Management Unit or TLMU, which is basically an
extended memory controller with reconfiguration support at runtime. Using the
TLMU enables the memory to be configured and reconfigured according to all
supported modes shown in (Table 7.1) and supports memory module isolation and
power management.
The syndrome acts as a control and monitoring unit for the TLMU. On the one
hand, the syndrome configures the TLMU, but on the other hand, it also shows the
current state, i.e., whether faults were detected.
ERA#processor#
Interfacing#zone###############################Interconnec7on#bus##
RAM#
RAM#
RAM#
RAM#
Passive#zone#
Ac7ve#zone#
Idle#memory#
Configured##memory#
T)logic#elements#
Fig. 7.15 Illustration of T-logic connector use
96
7 Testing, Checking, and Hardware Syndrome
Configuration Mechanism
Until now we just showed the properties and advantages of such a configurable
memory controller. What we did not explain is how such a controller could be
implemented while still providing interconnection and dynamic exclusion of faulty
components from the operational system.
For this, we suggest to use a so-called T-logic inter-connector, illustrated in
Fig. 7.15, an idealized concept of a hardware switch in the form of a “T” that can
connect or disconnect (for fault containment) from the memory controller by
“rotating”.
This logic is used in the hardware architecture to form a hardware configuration
scheme adjustable to the software or hardware requirements when a hardware
element itself detects faults and thus can’t be involved in further program execution
either on a temporary or permanent basis.
The four T-logic inter-connectors, one per memory module, are physically
contained in the T-logic Management Unit or TLMU, which is basically an
extended memory controller with reconfiguration support at runtime. Using the
TLMU enables the memory to be configured and reconfigured according to all
supported modes shown in (Table 7.1) and supports memory module isolation and
power management.
The syndrome acts as a control and monitoring unit for the TLMU. On the one
hand, the syndrome configures the TLMU, but on the other hand, it also shows the
current state, i.e., whether faults were detected.
ERA#processor#
Interfacing#zone###############################Interconnec7on#bus##
RAM#
RAM#
RAM#
RAM#
Passive#zone#
Ac7ve#zone#
Idle#memory#
Configured##memory#
T)logic#elements#
Fig. 7.15 Illustration of T-logic connector use
96
7 Testing, Checking, and Hardware Syndrome