9 Side Channel Assessment Platforms and Tools for Ubiquitous Systems
159
Fig. 9.1 General architecture
6 Control FPGA of the Sakura-X board), residing in the same FPGA. With
this approach, the softcore microprocessor undertakes the duty of control and
communication with the Cryptographic FPGA, through a hardware Finite State
Machine implemented inside the control interface, which utilizes a custom hardware
protocol between the two FPGAs. Data inputs to the DUT can be provided by the
softcore processor, as well as from a hardware Pseudo Random Generator (PRNG)
module (to support TVLA leakage assessment scenarios). The communication
between the two FPGAs is performed using a 16-bit address bus, a 16-bit data bus
for sending data to the crypto side and a 16-bit data bus for receiving data from the
Cryptographic FPGA side.
The use of an embedded system design inside the control FPGA provides support
for the proposed three-step trace collection approach thus allowing the execution
of a software API on the microprocessor for the realization of the trace collection
control loop. This API consists of reusable code functions that fit multiple trace
collection scenarios and DUTs. Through these functions the control FPGA remains
unchanged (no need for redesign or reprogram), regardless of the DUT inside the
cryptographic FPGA, as it can be quickly reconfigured only by passing certain
values to software registers inside the control interface. By setting code values to
these registers, the control interface’s Finite State Machine is ready to serve any
updated cryptographic component inside the cryptographic FPGA. In this way, the
control component can be permanently be downloaded inside the control FPGA’s
flash memory, thus negating the inflexibility issues that other hardware control loops
present in their adaptability to different DUTs and scenarios.
The above-mentioned software API provides functions that, beside the initialization of the control loop, set up the leakage trace collection parameters
(inputs/outputs number, bit-length, randomness), trigger encryption/decryption,
send or receive plaintext/ciphertext values to FIFOs, and register and randomize
159
Fig. 9.1 General architecture
6 Control FPGA of the Sakura-X board), residing in the same FPGA. With
this approach, the softcore microprocessor undertakes the duty of control and
communication with the Cryptographic FPGA, through a hardware Finite State
Machine implemented inside the control interface, which utilizes a custom hardware
protocol between the two FPGAs. Data inputs to the DUT can be provided by the
softcore processor, as well as from a hardware Pseudo Random Generator (PRNG)
module (to support TVLA leakage assessment scenarios). The communication
between the two FPGAs is performed using a 16-bit address bus, a 16-bit data bus
for sending data to the crypto side and a 16-bit data bus for receiving data from the
Cryptographic FPGA side.
The use of an embedded system design inside the control FPGA provides support
for the proposed three-step trace collection approach thus allowing the execution
of a software API on the microprocessor for the realization of the trace collection
control loop. This API consists of reusable code functions that fit multiple trace
collection scenarios and DUTs. Through these functions the control FPGA remains
unchanged (no need for redesign or reprogram), regardless of the DUT inside the
cryptographic FPGA, as it can be quickly reconfigured only by passing certain
values to software registers inside the control interface. By setting code values to
these registers, the control interface’s Finite State Machine is ready to serve any
updated cryptographic component inside the cryptographic FPGA. In this way, the
control component can be permanently be downloaded inside the control FPGA’s
flash memory, thus negating the inflexibility issues that other hardware control loops
present in their adaptability to different DUTs and scenarios.
The above-mentioned software API provides functions that, beside the initialization of the control loop, set up the leakage trace collection parameters
(inputs/outputs number, bit-length, randomness), trigger encryption/decryption,
send or receive plaintext/ciphertext values to FIFOs, and register and randomize