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A. P. Fournaris et al.
phase does not include any non-trivial transmission delays between the control loop
entity (i.e., the microcontroller) and the DUT, since the bus connecting them is
extremely fast, in contrast to the PC-based control loop where such transmission
is done serially. During execution, the microcontroller control loop is responsible
for transmitting the appropriate signals to the DUT so as to execute one or multiple
times a security/cryptography operation as well as to generate appropriate trigger
signals for trace collection by a DSO.
In the final step of the proposed control trace collection process, denoted as the
trace processing phase, the execution of the experiment has been concluded and the
experiment traces have been collected by the DSO. In this phase, post-collection
operations are performed on the collected traces, like averaging and alignment but
also operations related to the specificities of a particular experiment. This phase is
performed on the DSO or on a PC with an appropriate digital signal processing
toolbox, and it can be slow (depending on the post-collection operations that are
executed). However, the performance delay is considerably smaller than when a PC
is included in the control loop during an experiment.
9.4 A Use Case of a Flexible and Fast Platform for DUT SCA
Evaluation
To showcase the applicability and effectiveness of the above-proposed three-step
trace collection architecture and mechanism in action, we focus on the Flexible
Leakage Collection (FlexLeco) project, which was recently published in [427]. the
FlexLeco project was designed to match the latest trace collection challenges and
to introduce a unified mechanism for applying various trace collection scenarios. It
provides an architecture that tries to blend the reconfigurability of Software Control
loops with the speed of Hardware Control loops. Taking advantage of the latest
trace collection boards that utilize schemes with two FPGAs (one acting as the
Control Unit and the other as the Device Under Test), the project created two generic
hardware interfaces that enable fast communication between the two FPGAs, and
managed to include an embedded softcore processor inside the Control FPGA,
which is in charge of the Control Loop during the execution of trace collection
scenarios. The project is currently instantiated on the boards of the Sakura/Sasebo
project (Sakura-X and Sakura-G), but it can be modified to fit any board that adopts
the approach of two distinct, hardware-isolated FPGA chips.
The FlexLeco architecture of Fig. 9.1, consists of two generic interfaces and an
embedded softcore processor. Inside the Cryptographic FPGA a generic cryptographic interface is implemented for the communication of the Control Unit with the
DUT. This interface contains two variable memory spaces (called “Hyperegisters”)
that handle the inputs and outputs of the DUT.
Inside the control FPGA exists a generic control interface that is directly
connected with the embedded microprocessor (a Xilinx Microblaze for the Spartan-
A. P. Fournaris et al.
phase does not include any non-trivial transmission delays between the control loop
entity (i.e., the microcontroller) and the DUT, since the bus connecting them is
extremely fast, in contrast to the PC-based control loop where such transmission
is done serially. During execution, the microcontroller control loop is responsible
for transmitting the appropriate signals to the DUT so as to execute one or multiple
times a security/cryptography operation as well as to generate appropriate trigger
signals for trace collection by a DSO.
In the final step of the proposed control trace collection process, denoted as the
trace processing phase, the execution of the experiment has been concluded and the
experiment traces have been collected by the DSO. In this phase, post-collection
operations are performed on the collected traces, like averaging and alignment but
also operations related to the specificities of a particular experiment. This phase is
performed on the DSO or on a PC with an appropriate digital signal processing
toolbox, and it can be slow (depending on the post-collection operations that are
executed). However, the performance delay is considerably smaller than when a PC
is included in the control loop during an experiment.
9.4 A Use Case of a Flexible and Fast Platform for DUT SCA
Evaluation
To showcase the applicability and effectiveness of the above-proposed three-step
trace collection architecture and mechanism in action, we focus on the Flexible
Leakage Collection (FlexLeco) project, which was recently published in [427]. the
FlexLeco project was designed to match the latest trace collection challenges and
to introduce a unified mechanism for applying various trace collection scenarios. It
provides an architecture that tries to blend the reconfigurability of Software Control
loops with the speed of Hardware Control loops. Taking advantage of the latest
trace collection boards that utilize schemes with two FPGAs (one acting as the
Control Unit and the other as the Device Under Test), the project created two generic
hardware interfaces that enable fast communication between the two FPGAs, and
managed to include an embedded softcore processor inside the Control FPGA,
which is in charge of the Control Loop during the execution of trace collection
scenarios. The project is currently instantiated on the boards of the Sakura/Sasebo
project (Sakura-X and Sakura-G), but it can be modified to fit any board that adopts
the approach of two distinct, hardware-isolated FPGA chips.
The FlexLeco architecture of Fig. 9.1, consists of two generic interfaces and an
embedded softcore processor. Inside the Cryptographic FPGA a generic cryptographic interface is implemented for the communication of the Control Unit with the
DUT. This interface contains two variable memory spaces (called “Hyperegisters”)
that handle the inputs and outputs of the DUT.
Inside the control FPGA exists a generic control interface that is directly
connected with the embedded microprocessor (a Xilinx Microblaze for the Spartan-