10 Signal Processing for Particle Detectors
481
need electrical contacts at the terminals of gates and channels (source and drain)
their size will be limited by the metallization dimensions.
As far as particle and photon detectors are concerned, further progress in digital
circuit technology, based on nanoscale nodes, will result in increased functionality
of the detector circuits, particularly those integrated with detectors, as long as they
are economically available from multi-project foundry services or as commercial
components. The development of multi-layer (3D) circuits for detectors has been
challenged by limited access to this technology, given the relatively small quantities
needed in physics experiments and high costs.
As far as the analogue front-end circuits for particle detectors are concerned, it
appears that CMOS will be less useful below the ~65 nm node (Sect. 10.9.1 and
Ref. [51]). In higher precision circuits, such as analogue to digital converters and
switched capacitor memories, the dynamic range is limited by the low power supply
voltages (one volt or less) at the upper end and by the kTC noise at the lower end.
Fortunately. the provision of thicker oxide devices on the same nanoscale platforms
leaves the choice of the operating voltage, the gate length and width to the designer
(as discussed in Sect. 10.9.1).
An interesting domain, outside of the CMOS mainstream, has been presented by
single-electron transistors (SETs), [67, 68]. Single electron transistors are devices
with a capacitance so small that a single electron can generate a measurable voltage
(above the thermal voltage). To be observable, the mean energy of the electron on the
capacitance must be several times larger than its thermal energy (kTC noise). This
sets an upper limit on the capacitance of the control electrode (gate) of the transistor
(and the sensor connected to the transistor) and on the operating temperature. From
Sect. 10.7 and Table 10.1, an upper limit for the capacitance at room temperature
would be 1 aF (10 −18 F). Alternatively, the temperature would have to be 300 mK, to
allow a capacitance in the range of ~1 fF. SETs, although known for more than three
decades, have not been considered suitable for integration due to large variability in
their fabrication.
SETs might be suitable as very sensitive electrometers for equally low capacitance sensors. That sensitivity is for the most part due to their low capacitance and in
part due to improved carrier transport properties. At 300 K they are not matched to
even the smallest pixels of present particle and photon detectors, and will be useful
only with an entirely new generation of very fine grained detectors operated at low
temperatures.
Acknowledgments The author is indebted to his colleagues, Gianluigi De Geronimo, Paul
O’Connor, Sergio Rescia, Bo Yu, and the late Pavel Rehak for many stimulating discussions and,
over time, for contributions of material that has contributed greatly to this article. In particular, most
of the induced signal simulations are due to Bo Yu, the circuits shown in Figs. 10.23, 10.30 and
10.31 originated in publications by Gianluigi De Geronimo and Paul O’Connor. Paul O’Connor
provided much of the material on CMOS scaling, and Sergio Rescia worked with the author on 1/f
and kTC noise calculations. Special thanks are to Anand Kandasamy for help with editing of the
manuscript and the figures.
481
need electrical contacts at the terminals of gates and channels (source and drain)
their size will be limited by the metallization dimensions.
As far as particle and photon detectors are concerned, further progress in digital
circuit technology, based on nanoscale nodes, will result in increased functionality
of the detector circuits, particularly those integrated with detectors, as long as they
are economically available from multi-project foundry services or as commercial
components. The development of multi-layer (3D) circuits for detectors has been
challenged by limited access to this technology, given the relatively small quantities
needed in physics experiments and high costs.
As far as the analogue front-end circuits for particle detectors are concerned, it
appears that CMOS will be less useful below the ~65 nm node (Sect. 10.9.1 and
Ref. [51]). In higher precision circuits, such as analogue to digital converters and
switched capacitor memories, the dynamic range is limited by the low power supply
voltages (one volt or less) at the upper end and by the kTC noise at the lower end.
Fortunately. the provision of thicker oxide devices on the same nanoscale platforms
leaves the choice of the operating voltage, the gate length and width to the designer
(as discussed in Sect. 10.9.1).
An interesting domain, outside of the CMOS mainstream, has been presented by
single-electron transistors (SETs), [67, 68]. Single electron transistors are devices
with a capacitance so small that a single electron can generate a measurable voltage
(above the thermal voltage). To be observable, the mean energy of the electron on the
capacitance must be several times larger than its thermal energy (kTC noise). This
sets an upper limit on the capacitance of the control electrode (gate) of the transistor
(and the sensor connected to the transistor) and on the operating temperature. From
Sect. 10.7 and Table 10.1, an upper limit for the capacitance at room temperature
would be 1 aF (10 −18 F). Alternatively, the temperature would have to be 300 mK, to
allow a capacitance in the range of ~1 fF. SETs, although known for more than three
decades, have not been considered suitable for integration due to large variability in
their fabrication.
SETs might be suitable as very sensitive electrometers for equally low capacitance sensors. That sensitivity is for the most part due to their low capacitance and in
part due to improved carrier transport properties. At 300 K they are not matched to
even the smallest pixels of present particle and photon detectors, and will be useful
only with an entirely new generation of very fine grained detectors operated at low
temperatures.
Acknowledgments The author is indebted to his colleagues, Gianluigi De Geronimo, Paul
O’Connor, Sergio Rescia, Bo Yu, and the late Pavel Rehak for many stimulating discussions and,
over time, for contributions of material that has contributed greatly to this article. In particular, most
of the induced signal simulations are due to Bo Yu, the circuits shown in Figs. 10.23, 10.30 and
10.31 originated in publications by Gianluigi De Geronimo and Paul O’Connor. Paul O’Connor
provided much of the material on CMOS scaling, and Sergio Rescia worked with the author on 1/f
and kTC noise calculations. Special thanks are to Anand Kandasamy for help with editing of the
manuscript and the figures.