478
V. Radeka
same wafer an oxide thickness of ~5 nm, that requires a minimum channel length of
~250 nm and allows a supply voltage of ~2.5 V. This will make possible in a single
ASIC both high density digital circuits with the minimum feature size, and higher
voltage input/output circuits and precision analogue circuits with an effectively
larger feature size.
Analog design below 100 nm becomes gradually more difficult. The complexity
of ASIC design rules and the costs of the design tools increase steeply as the feature
size is reduced. This is discussed in some detail in Ref. [51].
While the developments in electronics technology have already made possible
very large and complex detectors, the power dissipation associated with increasingly
complex signal and data processing has been a problem and will remain a principal
limitation and challenge.
Along with the quest in the CMOS scaling continuing down to the nodes in the ~7
to 28 nm range, an additional path to higher circuit densities and to higher speed of
digital circuits (by shortening the interconnections) is three-dimensional integration
of several thin layers of CMOS circuits [52, 53]. A significant breakthrough in
particle and photon silicon detectors will be integration (by direct bonding) of a
thick (50–500 μm) high resistivity p-i-n detector die to one or more thin (~10 μm)
CMOS layers of readout electronics.
10.9.2 Transistors at Low Temperatures: Applications
in Future Detectors
Most of the electronics for particle detectors has been based on silicon CMOS
devices following the trends in electronics industry. Over the last two decades the
technology of silicon–germanium heterojunction bipolar transistors (SiGe HBT)
has been developed [54]. These devices have some key properties superior to
the bipolar junction transistor (BJT), notably a much higher current gain and
a much higher unity-gain frequency. The HBT, unlike the BJT can operate at
liquid nitrogen temperature, and furthermore, with an increased current gain.
Recently emerging cryogenic applications have generated renewed interest in low
temperature properties of both CMOS and HBT technologies [54, 55]. As with
HBTs, it has been found that various CMOS device properties improve at low
temperatures. The mobility and the transconductance increase by a factor of two
to three as the temperature decreases from 300 K to 43 K, and the (inverse)
subthreshold slope decreases from ~90 mV/decade to ~20 mV/decade resulting in
a higher ratio of the transconductance to the drain current. The transistor (series)
thermal noise has been observed to decrease monotonically from 300 K to 40 K [56].
There is one caveat: CMOS transistors have to be operated (at any temperature)
under conditions where hot electron generation, which is more pronounced at low
temperatures, is minimized [57].
V. Radeka
same wafer an oxide thickness of ~5 nm, that requires a minimum channel length of
~250 nm and allows a supply voltage of ~2.5 V. This will make possible in a single
ASIC both high density digital circuits with the minimum feature size, and higher
voltage input/output circuits and precision analogue circuits with an effectively
larger feature size.
Analog design below 100 nm becomes gradually more difficult. The complexity
of ASIC design rules and the costs of the design tools increase steeply as the feature
size is reduced. This is discussed in some detail in Ref. [51].
While the developments in electronics technology have already made possible
very large and complex detectors, the power dissipation associated with increasingly
complex signal and data processing has been a problem and will remain a principal
limitation and challenge.
Along with the quest in the CMOS scaling continuing down to the nodes in the ~7
to 28 nm range, an additional path to higher circuit densities and to higher speed of
digital circuits (by shortening the interconnections) is three-dimensional integration
of several thin layers of CMOS circuits [52, 53]. A significant breakthrough in
particle and photon silicon detectors will be integration (by direct bonding) of a
thick (50–500 μm) high resistivity p-i-n detector die to one or more thin (~10 μm)
CMOS layers of readout electronics.
10.9.2 Transistors at Low Temperatures: Applications
in Future Detectors
Most of the electronics for particle detectors has been based on silicon CMOS
devices following the trends in electronics industry. Over the last two decades the
technology of silicon–germanium heterojunction bipolar transistors (SiGe HBT)
has been developed [54]. These devices have some key properties superior to
the bipolar junction transistor (BJT), notably a much higher current gain and
a much higher unity-gain frequency. The HBT, unlike the BJT can operate at
liquid nitrogen temperature, and furthermore, with an increased current gain.
Recently emerging cryogenic applications have generated renewed interest in low
temperature properties of both CMOS and HBT technologies [54, 55]. As with
HBTs, it has been found that various CMOS device properties improve at low
temperatures. The mobility and the transconductance increase by a factor of two
to three as the temperature decreases from 300 K to 43 K, and the (inverse)
subthreshold slope decreases from ~90 mV/decade to ~20 mV/decade resulting in
a higher ratio of the transconductance to the drain current. The transistor (series)
thermal noise has been observed to decrease monotonically from 300 K to 40 K [56].
There is one caveat: CMOS transistors have to be operated (at any temperature)
under conditions where hot electron generation, which is more pronounced at low
temperatures, is minimized [57].