160
G. Lutz and R. Klanner
Fig. 5.18 Single channel readout schematics of the CAMEX64 strip-detector readout circuit
collider experiments. A variety of circuits has been developed for this purpose, the
basic principle of essentially all of them being: (1) parallel amplification using a
charge-sensitive amplifier at each input; (2) parallel signal filtering combined with
second-stage amplification and parallel storage within capacitive hold circuits; and
(3) serial readout through one single output channel.
We will present only one of the developments [16]. This was not only one of
the first to be started but is still in use and has been further developed for many
important applications.
The basic functional principle of a single channel is shown in Fig. 5.18. It
consists of two charge-sensitive amplifiers, each followed by a source follower, and
four sets of capacitors and switches that connect the output of the first amplifier
with the input of the second amplifier. The circuit is rather similar to the one
shown in Fig. 5.17, but the essential difference is the fourfold multiplication of
the capacitive coupling between the amplifiers. In this way it is possible to perform
fourfold double-correlated sampling at times that are shifted relative to each other.
This procedure provides a good approximation to trapezoidal shaping, which means
averaging the output over time intervals before and after signal arrival and taking
the difference between the averaged samples.
The switching sequence that performs this function is the following: (1) Close
R 1 and R 2 . The charges on the feedback capacitances C f1 and C f2 are cleared. (2)
Open R 1 : some (unwanted) charge will be injected into the input by the switching
procedure, producing an offset in U 1. (3) Close and open in sequence S 1 to S 4 .
The U 1 offset values at the four times t 1 to t 4 will be stored on the four capacitors
C s . (4) Open switch R 2 . A small offset voltage appears at the output. (5) Deposit
signal charge Q sig at input. U 1 changes by an amount of U 1 = Q sig /C f1 . (6) Close
and open S 1 to S 4 in sequence at times t 1 to t 4 . A charge C s U 1 is inserted into
the second amplifier at each sample. The total output voltage is 4C s U 1 /C f2 =
Q sig 4C s /(C f1 C f2 ).
The complete chip, containing 64 channels, also comprises additional electronics, as shown in Fig. 5.19. Three test inputs allow injection of a defined charge
through test capacitors. Digital steering signals are regenerated by comparators. The
G. Lutz and R. Klanner
Fig. 5.18 Single channel readout schematics of the CAMEX64 strip-detector readout circuit
collider experiments. A variety of circuits has been developed for this purpose, the
basic principle of essentially all of them being: (1) parallel amplification using a
charge-sensitive amplifier at each input; (2) parallel signal filtering combined with
second-stage amplification and parallel storage within capacitive hold circuits; and
(3) serial readout through one single output channel.
We will present only one of the developments [16]. This was not only one of
the first to be started but is still in use and has been further developed for many
important applications.
The basic functional principle of a single channel is shown in Fig. 5.18. It
consists of two charge-sensitive amplifiers, each followed by a source follower, and
four sets of capacitors and switches that connect the output of the first amplifier
with the input of the second amplifier. The circuit is rather similar to the one
shown in Fig. 5.17, but the essential difference is the fourfold multiplication of
the capacitive coupling between the amplifiers. In this way it is possible to perform
fourfold double-correlated sampling at times that are shifted relative to each other.
This procedure provides a good approximation to trapezoidal shaping, which means
averaging the output over time intervals before and after signal arrival and taking
the difference between the averaged samples.
The switching sequence that performs this function is the following: (1) Close
R 1 and R 2 . The charges on the feedback capacitances C f1 and C f2 are cleared. (2)
Open R 1 : some (unwanted) charge will be injected into the input by the switching
procedure, producing an offset in U 1. (3) Close and open in sequence S 1 to S 4 .
The U 1 offset values at the four times t 1 to t 4 will be stored on the four capacitors
C s . (4) Open switch R 2 . A small offset voltage appears at the output. (5) Deposit
signal charge Q sig at input. U 1 changes by an amount of U 1 = Q sig /C f1 . (6) Close
and open S 1 to S 4 in sequence at times t 1 to t 4 . A charge C s U 1 is inserted into
the second amplifier at each sample. The total output voltage is 4C s U 1 /C f2 =
Q sig 4C s /(C f1 C f2 ).
The complete chip, containing 64 channels, also comprises additional electronics, as shown in Fig. 5.19. Three test inputs allow injection of a defined charge
through test capacitors. Digital steering signals are regenerated by comparators. The