Tile
Router
≈10
mm
2.5 mm
2.5 mm
≈20 mm
78
Network-on-Chip
Figure 4.4
Possible distribution of cores, routers, and links in a 4 × 4 MoT structure with two cores to each
Leaf router.
network structure, critical path delay of a router increases with increasing node
degree. This happens as the routing logic and arbitration complexity increase
with increasing node degree. Hence, in a network, the router with a highest
node degree has the minimum frequency. To support mesochronous clocking,
the clock having minimum frequency is applied to all the routers of a network.
Table 4.1 shows the clock frequencies of different types of wormhole (WH)
routers used in implementing the networks under consideration. Though MoT
has the highest minimum frequency, in this work, to provide a consistent comparison with other networks, all the routers are driven at 1.5-GHz clock.
For evaluating the performance of these networks, a SystemC-based cycleaccurate NoC simulator has been developed. The simulator operates at the
granularity of individual architectural components of the router. It supports
mesochronous clocking strategy where the routers are driven by the same
clock frequency with varying phase.
4.1.1 Performance Metrics
The performance of an on-chip communication network is characterized
by its throughput and latency. Throughput is the maximum accepted traffic from the network and it is related to the peak data rate sustainable by
the network. Although the ratio of the number of edges (E) and the average
distance (D) of a particular network is a good indicator of throughput in
contention-free traffic, in an actual traffic scenario, the average time spent
by the flits in the network will increase due to traffic congestion, and hence
throughput and latency values will differ from their theoretical counterparts. In this book, throughput is defined as (Pande et al. 2005)
Total packets completed × Packet length
Throughput =
(4.1)
Number of IP bloc cks × Total time
Router
≈10
mm
2.5 mm
2.5 mm
≈20 mm
78
Network-on-Chip
Figure 4.4
Possible distribution of cores, routers, and links in a 4 × 4 MoT structure with two cores to each
Leaf router.
network structure, critical path delay of a router increases with increasing node
degree. This happens as the routing logic and arbitration complexity increase
with increasing node degree. Hence, in a network, the router with a highest
node degree has the minimum frequency. To support mesochronous clocking,
the clock having minimum frequency is applied to all the routers of a network.
Table 4.1 shows the clock frequencies of different types of wormhole (WH)
routers used in implementing the networks under consideration. Though MoT
has the highest minimum frequency, in this work, to provide a consistent comparison with other networks, all the routers are driven at 1.5-GHz clock.
For evaluating the performance of these networks, a SystemC-based cycleaccurate NoC simulator has been developed. The simulator operates at the
granularity of individual architectural components of the router. It supports
mesochronous clocking strategy where the routers are driven by the same
clock frequency with varying phase.
4.1.1 Performance Metrics
The performance of an on-chip communication network is characterized
by its throughput and latency. Throughput is the maximum accepted traffic from the network and it is related to the peak data rate sustainable by
the network. Although the ratio of the number of edges (E) and the average
distance (D) of a particular network is a good indicator of throughput in
contention-free traffic, in an actual traffic scenario, the average time spent
by the flits in the network will increase due to traffic congestion, and hence
throughput and latency values will differ from their theoretical counterparts. In this book, throughput is defined as (Pande et al. 2005)
Total packets completed × Packet length
Throughput =
(4.1)
Number of IP bloc cks × Total time